E. Sotiriades, C. Kozanitis, Grigorios Chrysos, A. Dollas
In the course of rapid system prototyping of a large scale design and implementation of the BLAST algorithm for bioinformatics, we evaluated two different design methods. First, we used the "traditional" method of design with modeling in C and design and synthesis using VHDL. Second, we used the automated tools MATLAB/Simulink with two different design flows, i.e. the fully automated one from MATLAB to bitstream, and, the architecture and subsystem development based on the MATLAB/Simulink results. We examine the tradeoffs between designer time, design quality and speed, and resource optimization. We analyze how modern tools such as MATLAB/Simulink can improve architecture design and facilitate "what if" scenarios. We conclude that conventional architecture development and design flow is still required for highly optimized system building but the architecture development capabilities of modern tools need to be assimilated in the design process
{"title":"Rapid Phototyping of a System-on-a-Chip for the BLAST Algorithm Implementation","authors":"E. Sotiriades, C. Kozanitis, Grigorios Chrysos, A. Dollas","doi":"10.1109/RSP.2006.31","DOIUrl":"https://doi.org/10.1109/RSP.2006.31","url":null,"abstract":"In the course of rapid system prototyping of a large scale design and implementation of the BLAST algorithm for bioinformatics, we evaluated two different design methods. First, we used the \"traditional\" method of design with modeling in C and design and synthesis using VHDL. Second, we used the automated tools MATLAB/Simulink with two different design flows, i.e. the fully automated one from MATLAB to bitstream, and, the architecture and subsystem development based on the MATLAB/Simulink results. We examine the tradeoffs between designer time, design quality and speed, and resource optimization. We analyze how modern tools such as MATLAB/Simulink can improve architecture design and facilitate \"what if\" scenarios. We conclude that conventional architecture development and design flow is still required for highly optimized system building but the architecture development capabilities of modern tools need to be assimilated in the design process","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115041130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniel Cheung-Foo-Wo, J. Tigli, S. Lavirotte, M. Riveill
This paper presents Wcomp which is a framework for rapid application prototyping. This framework has been developed for targeting wearable computing applications but can also be used in the field of pervasive and context-aware computing. In the first part of the paper, we investigate the possibility of taking into consideration the relations between software components and resources of the "operating context" in our Wcomp platform. Secondly, we investigate the opportunity of taking a multi-designer approach in order to adapt the application to multiple well-suited representations. Then we introduce in the platform a new design approach based on patterns of interactions called ISL4Wcomp
{"title":"Wcomp: a Multi-Design Approach for Prototyping Applications using Heterogeneous Resources","authors":"Daniel Cheung-Foo-Wo, J. Tigli, S. Lavirotte, M. Riveill","doi":"10.1109/RSP.2006.42","DOIUrl":"https://doi.org/10.1109/RSP.2006.42","url":null,"abstract":"This paper presents Wcomp which is a framework for rapid application prototyping. This framework has been developed for targeting wearable computing applications but can also be used in the field of pervasive and context-aware computing. In the first part of the paper, we investigate the possibility of taking into consideration the relations between software components and resources of the \"operating context\" in our Wcomp platform. Secondly, we investigate the opportunity of taking a multi-designer approach in order to adapt the application to multiple well-suited representations. Then we introduce in the platform a new design approach based on patterns of interactions called ISL4Wcomp","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126186660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As embedded systems increase in complexity, rapid performance estimation methods, appropriate for use early in the design process, are becoming more and more necessary. These methods can produce significant decreases in execution time, power consumption and system cost. However, to be practicable, a design space exploration (DSE) process must be capable of evaluating several design alternatives quickly. This paper focuses on ways to accelerate performance and power consumption evaluation for embedded systems. Three methods: statistical simulation (SS), analytical modeling and detailed simulation (AMDS) and analytical modeling and statistical simulation (AMSS), offering both speed and accuracy for detailed cycle-accurate micro-architecture simulation, are presented and compared. Experimental results indicate that these methods produce interesting simulation acceleration factors. In addition, the error margin is on average less than 3.8%, reaching 8% in the worst case
{"title":"Rapid Performance and Power Consumption Estimation Methods for Embedded System Design","authors":"S. Niar, Nicolas Inglart","doi":"10.1109/RSP.2006.30","DOIUrl":"https://doi.org/10.1109/RSP.2006.30","url":null,"abstract":"As embedded systems increase in complexity, rapid performance estimation methods, appropriate for use early in the design process, are becoming more and more necessary. These methods can produce significant decreases in execution time, power consumption and system cost. However, to be practicable, a design space exploration (DSE) process must be capable of evaluating several design alternatives quickly. This paper focuses on ways to accelerate performance and power consumption evaluation for embedded systems. Three methods: statistical simulation (SS), analytical modeling and detailed simulation (AMDS) and analytical modeling and statistical simulation (AMSS), offering both speed and accuracy for detailed cycle-accurate micro-architecture simulation, are presented and compared. Experimental results indicate that these methods produce interesting simulation acceleration factors. In addition, the error margin is on average less than 3.8%, reaching 8% in the worst case","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Melissa Vetromille, Luciano Ost, C. Marcon, C. Reif, Fabiano Hessel
In order to enhance performance and improve predictability of the real time systems, implementing some critical operating system functionalities, like time management and task scheduling, in software and others in hardware is an interesting approach. Scheduling decision for real-time embedded software applications is an important problem in real-time operating system (RTOS) and has a great impact on system performance. In this paper, we evaluate the pros and cons of migrating RTOS scheduler implementation from software to hardware. We investigate three different RTOS scheduler implementation approaches: (i) implemented in software running in the same processor of the application tasks, (ii) implemented in software running in a co-processor, and (iii) implemented in hardware, while application tasks are running on a processor. We demonstrate the effectiveness of each approach by simulating and analyzing a set of benchmarks representing different embedded application classes
{"title":"RTOS Scheduler Implementation in Hardware and Software for Real Time Applications","authors":"Melissa Vetromille, Luciano Ost, C. Marcon, C. Reif, Fabiano Hessel","doi":"10.1109/RSP.2006.34","DOIUrl":"https://doi.org/10.1109/RSP.2006.34","url":null,"abstract":"In order to enhance performance and improve predictability of the real time systems, implementing some critical operating system functionalities, like time management and task scheduling, in software and others in hardware is an interesting approach. Scheduling decision for real-time embedded software applications is an important problem in real-time operating system (RTOS) and has a great impact on system performance. In this paper, we evaluate the pros and cons of migrating RTOS scheduler implementation from software to hardware. We investigate three different RTOS scheduler implementation approaches: (i) implemented in software running in the same processor of the application tasks, (ii) implemented in software running in a co-processor, and (iii) implemented in hardware, while application tasks are running on a processor. We demonstrate the effectiveness of each approach by simulating and analyzing a set of benchmarks representing different embedded application classes","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130298480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Using domain specific modeling (DSM) allows solutions to be expressed in the idiom and at the level of abstraction of the problem domain. However, this does not imply that prototypes can be easily and rapidly generated. In reality, domain specific languages (DSLs) are difficult to design, implement and maintain, and usually there is a potential loss of efficiency when compared with hand-coded software. In this paper we explain the principles based on which we expect to solve some of these problems by means of transformation from a DSL to a formalism with a well define semantics named concurrent object oriented Petri-nets (CO-OPN). The proposed methodology uses the metamodel of the DSL as the principle for the transformation. This transformation represents the semantic mapping between the DSL and CO-OPN. The achievement is both to provide a formally defined semantics to the DSL and, since CO-OPN is integrated in a framework, to provide the functionalities that allow model verification and fast prototype generation for the DSL
{"title":"Principles for System Prototype and Verification Using Metamodel Based Transformations","authors":"Luis Pedro, L. Lucio, Didier Buchs","doi":"10.1109/RSP.2006.29","DOIUrl":"https://doi.org/10.1109/RSP.2006.29","url":null,"abstract":"Using domain specific modeling (DSM) allows solutions to be expressed in the idiom and at the level of abstraction of the problem domain. However, this does not imply that prototypes can be easily and rapidly generated. In reality, domain specific languages (DSLs) are difficult to design, implement and maintain, and usually there is a potential loss of efficiency when compared with hand-coded software. In this paper we explain the principles based on which we expect to solve some of these problems by means of transformation from a DSL to a formalism with a well define semantics named concurrent object oriented Petri-nets (CO-OPN). The proposed methodology uses the metamodel of the DSL as the principle for the transformation. This transformation represents the semantic mapping between the DSL and CO-OPN. The achievement is both to provide a formally defined semantics to the DSL and, since CO-OPN is integrated in a framework, to provide the functionalities that allow model verification and fast prototype generation for the DSL","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129605312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The generation tool employ a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where the maximum number of non-zero in each coefficient is taken as a constraint, followed by common subexpression elimination (CSE) among multipliers. Synthesis results for a range of different filter specifications, using Quartus II FPGA synthesis tool are presented
本文介绍了一种方法的生成工具和性能结果，该方法可以最大限度地减少实现用于高性能硬连线(固定系数)实现的并行数字有限脉冲响应(FIR)滤波器所需的硬件数量。生成工具采用两种方法的组合:首先，将系数简化为n- 2的幂(NPT)项，其中每个系数中非零的最大数目作为约束，然后在乘数之间进行公共子表达式消除(CSE)。给出了使用Quartus II FPGA合成工具对一系列不同规格滤波器的合成结果
{"title":"A High Performance Parallel FIR Filters Generation Tool","authors":"V. S. Rosa, E. Costa, S. Bampi","doi":"10.1109/RSP.2006.2","DOIUrl":"https://doi.org/10.1109/RSP.2006.2","url":null,"abstract":"This paper presents generation tool and performance results on a method to minimize the amount of hardware needed to implement a parallel digital finite impulse response (FIR) filters for hardwired (fixed coefficients) implementation targeted for high performance. The generation tool employ a combination of two approaches: first, the reduction of the coefficients to n-power-of-two (NPT) terms, where the maximum number of non-zero in each coefficient is taken as a constraint, followed by common subexpression elimination (CSE) among multipliers. Synthesis results for a range of different filter specifications, using Quartus II FPGA synthesis tool are presented","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128069684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Virtual machine technology allows for the reuse of applications and code over various heterogeneous platforms. A virtual machine simply adds another layer of abstraction between the application and the native hardware. A major drawback of an application running on a virtual machine, however, is that the performance is below that of an application targeted for a native platform. Previous work has dealt with improving the performance of a virtual machine through hardware support using field programmable gate arrays (FPGAs). With the growing capacities of FPGAs it is becoming possible to provide higher levels of hardware support. This work examines the Java virtual machine (JVM), by implementing it in hardware, using a network-on-chip (NoC) design methodology. A subset of the JVM instructions are implemented in a hardware engine, with the more complex operations performed in software, and this hardware engine is replicated numerous times within the FPGA. By having several JVM instances execute in hardware concurrently, multiple applications and/or threads can simultaneously benefit from hardware implementation
{"title":"An Embedded Java Virtual Machine Using Network-on-Chip Design","authors":"Graham Mathias, K. Kent","doi":"10.1109/RSP.2006.7","DOIUrl":"https://doi.org/10.1109/RSP.2006.7","url":null,"abstract":"Virtual machine technology allows for the reuse of applications and code over various heterogeneous platforms. A virtual machine simply adds another layer of abstraction between the application and the native hardware. A major drawback of an application running on a virtual machine, however, is that the performance is below that of an application targeted for a native platform. Previous work has dealt with improving the performance of a virtual machine through hardware support using field programmable gate arrays (FPGAs). With the growing capacities of FPGAs it is becoming possible to provide higher levels of hardware support. This work examines the Java virtual machine (JVM), by implementing it in hardware, using a network-on-chip (NoC) design methodology. A subset of the JVM instructions are implemented in a hardware engine, with the more complex operations performed in software, and this hardware engine is replicated numerous times within the FPGA. By having several JVM instances execute in hardware concurrently, multiple applications and/or threads can simultaneously benefit from hardware implementation","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128350946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. J. Lobo, M. Freire, M. Garrido, C. Sanz, F. Pescador, D. S. Martínez
In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over digital audio broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a personal computer via an USB port. We have implemented the system on an FPGA with an embedded RISC processor. We also describe the tools whose development was needed to ease the IP extractor development and to test the functionality of the system. Finally the results of our tests with two applications of IP data transmission over DAB networks, data carousels and video streaming, are presented
{"title":"The Prototyping Methodology of a Data Receiver for Digital Audio Broadcasting (DAB) Networks","authors":"P. J. Lobo, M. Freire, M. Garrido, C. Sanz, F. Pescador, D. S. Martínez","doi":"10.1109/RSP.2006.41","DOIUrl":"https://doi.org/10.1109/RSP.2006.41","url":null,"abstract":"In this paper we describe the implementation methodology of a prototype for reception of IP datagrams transmitted over digital audio broadcasting (DAB) networks. The system reads the DAB ensemble from the RDI output of a DAB receiver, extracts the IP datagrams and feeds them to a personal computer via an USB port. We have implemented the system on an FPGA with an embedded RISC processor. We also describe the tools whose development was needed to ease the IP extractor development and to test the functionality of the system. Finally the results of our tests with two applications of IP data transmission over DAB networks, data carousels and video streaming, are presented","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128306419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
PSL is a standard formal language to specify logic and temporal properties in a declarative style, under the form of assertions. We defined a library of components, and an interconnection method to automatically synthesize hardware monitors that can be linked to a prototype of the design under verification, thus providing an efficient debugging platform. The existing tool produces on-line checkers that are clock synchronized with the monitored design. The on-going work aims at snooping the design with monitors built from asynchronous modules. The monitors are thus reliable in the case of truly asynchronous events, and become applicable to a wider range of verification tasks, notably the communications among globally asynchronous modules
{"title":"Asynchronous Assertion Monitors for multi-Clock Domain System Verification","authors":"K. Morin-Allory, L. Fesquet, D. Borrione","doi":"10.1109/RSP.2006.9","DOIUrl":"https://doi.org/10.1109/RSP.2006.9","url":null,"abstract":"PSL is a standard formal language to specify logic and temporal properties in a declarative style, under the form of assertions. We defined a library of components, and an interconnection method to automatically synthesize hardware monitors that can be linked to a prototype of the design under verification, thus providing an efficient debugging platform. The existing tool produces on-line checkers that are clock synchronized with the monitored design. The on-going work aims at snooping the design with monitors built from asynchronous modules. The monitors are thus reliable in the case of truly asynchronous events, and become applicable to a wider range of verification tasks, notably the communications among globally asynchronous modules","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124650697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process for the development and verification of statechart prototype models augmented with statechart assertions using the StateRover tool. The novel aspects of the proposed process include (1) writing formal specifications using statechart assertions, (2) JUnit-based simulation and validation of statechart assertions, (3) JUnit-based simulation and testing of statechart prototype models augmented with statechart assertions, (4) automatic, JUnit-based, white-box testing of statechart prototypes augmented with statechart assertions, and (5) spiral adjustment of model and specification using the test results. We demonstrate the proposed process with a prototype of a safety-critical computer assisted resuscitation algorithm (CARA) software for a casualty intravenous fluid infusion pump
{"title":"Creation and Validation of Embedded Assertion Statecharts","authors":"D. Drusinsky, M. Shing, K. Demir","doi":"10.1109/RSP.2006.12","DOIUrl":"https://doi.org/10.1109/RSP.2006.12","url":null,"abstract":"This paper addresses the need to integrate formal assertions into the modeling, implementation, and testing of statechart based designs. The paper describes an iterative process for the development and verification of statechart prototype models augmented with statechart assertions using the StateRover tool. The novel aspects of the proposed process include (1) writing formal specifications using statechart assertions, (2) JUnit-based simulation and validation of statechart assertions, (3) JUnit-based simulation and testing of statechart prototype models augmented with statechart assertions, (4) automatic, JUnit-based, white-box testing of statechart prototypes augmented with statechart assertions, and (5) spiral adjustment of model and specification using the test results. We demonstrate the proposed process with a prototype of a safety-critical computer assisted resuscitation algorithm (CARA) software for a casualty intravenous fluid infusion pump","PeriodicalId":113937,"journal":{"name":"Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128337915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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