优化的链接到布局流程,用于定时关键设计

S. Pallipatti, K. Ramabadran, S. Ayathu
{"title":"优化的链接到布局流程,用于定时关键设计","authors":"S. Pallipatti, K. Ramabadran, S. Ayathu","doi":"10.1109/MWSCAS.2000.952915","DOIUrl":null,"url":null,"abstract":"Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.","PeriodicalId":437349,"journal":{"name":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","volume":"2 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An optimized links-to-layout flow for timing critical designs\",\"authors\":\"S. Pallipatti, K. Ramabadran, S. Ayathu\",\"doi\":\"10.1109/MWSCAS.2000.952915\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.\",\"PeriodicalId\":437349,\"journal\":{\"name\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"volume\":\"2 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2000.952915\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2000.952915","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

数字设计的时序闭合流程称为链接到布局(LTL)流程。这个流的瓶颈导致了非最优设计。对于复杂的设计,时间关闭变得完全不可预测,并导致总体成本的显著增加,就模具面积和上市时间而言。解决这个问题的商业工具尚未得到充分验证,而且非常昂贵。定义、实现并验证了解决时间和区域问题的优化LTL流程。使用优化的LTL流程可显著改善设计周期时间(60%-70%),并获得出色的面积增益(7-10%)。
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An optimized links-to-layout flow for timing critical designs
Timing closure flow for digital designs is referred to as links-to-layout (LTL) flow. The bottlenecks with this flow leads to non-optimal designs. Timing closure becomes totally unpredictable for complex designs and leads to significant increase in overall cost, in terms of die-area and time-to-market. Commercial tools to solve this problem are not yet fully proven and are also very expensive. An optimized LTL flow that addresses the timing and area problems was defined, implemented and verified. Significant improvements in design cycle time (60%-70%) coupled with excellent area gains (7-10%) were obtained using the optimized LTL flow.
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