片上互连和协议栈,用于多种通信范式和编程模型

Andreas Hansson, K. Goossens
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引用次数: 27

摘要

越来越多的具有不同需求的应用程序以硬件和软件知识产权(IP)的形式集成在同一个片上系统(SoC)上。不同的需求,再加上由不相关的设计团队开发的ip,导致了片上互连必须适应的多种通信范例、编程模型和接口协议。传统上,片上总线通过已建立的内存一致性模型提供分布式共享内存通信,但与特定的接口协议紧密耦合。另一方面,片上网络提供分层和接口抽象,但以点对点流通信为中心,并且不解决协议堆栈中更高层的问题,例如内存一致性模型和消息依赖死锁。在这项工作中,我们介绍了一个片上互连和协议栈,它结合了流和分布式共享内存通信。提议的互连提供了一个已建立的内存一致性模型,并且不限制任何更高级别的协议依赖关系。我们提出了协议栈和架构块,并量化了块级和完整SoC的成本。对于具有多种通信范式和编程模型的多处理器多应用SoC,我们提出的互连仅占芯片面积的4%。
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An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate. Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-to-point streaming communication, and do not address issues at the higher layers in the protocol stack, such as memory-consistency models and message-dependent deadlock. In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.
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