使用直接电荷转移加法器的低失真双采样ΔΣ ADC

2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI:10.1109/SOCCON.2009.5398091

Yan Wang, G. Temes

{"title":"使用直接电荷转移加法器的低失真双采样ΔΣ ADC","authors":"Yan Wang, G. Temes","doi":"10.1109/SOCCON.2009.5398091","DOIUrl":null,"url":null,"abstract":"A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and simulated.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"46 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder\",\"authors\":\"Yan Wang, G. Temes\",\"doi\":\"10.1109/SOCCON.2009.5398091\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and simulated.\",\"PeriodicalId\":303505,\"journal\":{\"name\":\"2009 IEEE International SOC Conference (SOCC)\",\"volume\":\"46 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International SOC Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCCON.2009.5398091\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International SOC Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCCON.2009.5398091","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

提出了一种新的双采样架构，用于宽带低功耗ΔΣ ADC设计。采用直接电荷转移加法器降低了对加法器的带宽要求，并通过使用低失真拓扑放宽了环路滤波器的线性要求。为了验证所提出的设计方法，采用所提出的方案设计并仿真了一个二阶双采样delta-sigma ADC。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder

A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and simulated.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 IEEE International SOC Conference (SOCC)

自引率

0.00%

发文量