SOC chip scheduler embodying I-slip algorithm

We describe the methodology; the design and the implementation of scheduler block of interconnect. The scheduler block is implemented in Verilog using SYNOPSYS tool's DVE and Design_vision. The interconnect is capable of handling 72 bit packets and a total of 32 packets at a time. There are total 8 devices and we have to establish the communication between them. Each device consists of an input block and the output block. The input block first receives the 72 bit packet and the total of 32 packets one by one. The input block internally consists of four arrays-destination head, destination tail, packet array and linked list array and also a shift register. It stores the packets in an array called packet array. When scheduler sends transmit request these packets are given to the scheduler. Scheduler internally consists of grant and accept arbiters. Scheduler perform its operation in three steps i.e. request, grant and accept. It works on the principle of i-slip algorithm. Finally the scheduler decides that which packet should be send from the input block to the output block of the device. Output block of the device simply receives the packet. These packets are sent and received in two phases. In the first phase 36 bits are sent and in the second phase 36bits are sent. Thus the connection is established between the devices using interconnect. We are also modifying the scheduler design to reduce the area required for on chip implementation. For this reason we are combining the two sets of arbiters into only one, so the total arbiters required for modified scheduler now reduces to only 8 compared to 16 for original scheduler.