Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, M. Fujita
{"title":"使用高级设计描述的后硅调试支持","authors":"Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, M. Fujita","doi":"10.1109/ATS.2009.28","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A Post-Silicon Debug Support Using High-Level Design Description\",\"authors\":\"Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, M. Fujita\",\"doi\":\"10.1109/ATS.2009.28\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.\",\"PeriodicalId\":106283,\"journal\":{\"name\":\"2009 Asian Test Symposium\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Asian Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2009.28\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Asian Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2009.28","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Post-Silicon Debug Support Using High-Level Design Description
In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.
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