{"title":"基于SystemC规范的数字结构多版本并行综合","authors":"V. Obrizan, Tetiana Soklakova","doi":"10.1109/EWDTS.2016.7807664","DOIUrl":null,"url":null,"abstract":"This paper presents a multivesion parallel synthesis of digital structures based on SystemC specification. The purpose of which is a substantial reduction in design time computing architectures and increasing quality of digital products through multiversion synthesis structure of the digital products based on a predetermined specification in SystemC environments (C ++) and automatic selection of functional components by parallel synthesis and verification of system-level architectural decisions in accordance with proposed metric.","PeriodicalId":364686,"journal":{"name":"2016 IEEE East-West Design & Test Symposium (EWDTS)","volume":"175 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multiversion parallel synthesis of digital structures based on SystemC specification\",\"authors\":\"V. Obrizan, Tetiana Soklakova\",\"doi\":\"10.1109/EWDTS.2016.7807664\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a multivesion parallel synthesis of digital structures based on SystemC specification. The purpose of which is a substantial reduction in design time computing architectures and increasing quality of digital products through multiversion synthesis structure of the digital products based on a predetermined specification in SystemC environments (C ++) and automatic selection of functional components by parallel synthesis and verification of system-level architectural decisions in accordance with proposed metric.\",\"PeriodicalId\":364686,\"journal\":{\"name\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"volume\":\"175 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2016.7807664\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2016.7807664","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multiversion parallel synthesis of digital structures based on SystemC specification
This paper presents a multivesion parallel synthesis of digital structures based on SystemC specification. The purpose of which is a substantial reduction in design time computing architectures and increasing quality of digital products through multiversion synthesis structure of the digital products based on a predetermined specification in SystemC environments (C ++) and automatic selection of functional components by parallel synthesis and verification of system-level architectural decisions in accordance with proposed metric.
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