Y. Bai, D. Gaisbauer, S. Huber, I. Konorov, D. Levit, D. Steffen, S. Paul
{"title":"智能FPGA数据采集框架","authors":"Y. Bai, D. Gaisbauer, S. Huber, I. Konorov, D. Levit, D. Steffen, S. Paul","doi":"10.1109/rtc.2016.7543135","DOIUrl":null,"url":null,"abstract":"In this paper we present the FPGA-based framework IFDAQ which is used for the development of the data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of the IP cores written in VHDL which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of the SERDES-based TDC channels, an interface to a multi-channel 80MS/s 10-bit ADC, data transmission and synchronization protocol between FPGA, event builder and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front-end and data concentrator. This modular design also helps to scale and adapt the data acquisition system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the straw drift chambers and the electromagnetic calorimeters of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this upgrade.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"9 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Intelligent FPGA data acquisition framework\",\"authors\":\"Y. Bai, D. Gaisbauer, S. Huber, I. Konorov, D. Levit, D. Steffen, S. Paul\",\"doi\":\"10.1109/rtc.2016.7543135\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we present the FPGA-based framework IFDAQ which is used for the development of the data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of the IP cores written in VHDL which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of the SERDES-based TDC channels, an interface to a multi-channel 80MS/s 10-bit ADC, data transmission and synchronization protocol between FPGA, event builder and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front-end and data concentrator. This modular design also helps to scale and adapt the data acquisition system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the straw drift chambers and the electromagnetic calorimeters of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this upgrade.\",\"PeriodicalId\":383702,\"journal\":{\"name\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"volume\":\"9 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE-NPSS Real Time Conference (RT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/rtc.2016.7543135\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE-NPSS Real Time Conference (RT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/rtc.2016.7543135","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we present the FPGA-based framework IFDAQ which is used for the development of the data acquisition systems for detectors in high energy physics. The framework supports Xilinx FPGA and provides a collection of the IP cores written in VHDL which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of the SERDES-based TDC channels, an interface to a multi-channel 80MS/s 10-bit ADC, data transmission and synchronization protocol between FPGA, event builder and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front-end and data concentrator. This modular design also helps to scale and adapt the data acquisition system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the straw drift chambers and the electromagnetic calorimeters of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this upgrade.