K. Iwata, S. Mochizuki, Motoki Kimura, H. Ueda, Keisuke Matsumoto, Kazushi Akie, T. Shibayama, Hiroshi Hatae, Hiromi Watanabe
{"title":"80mw双视频编解码器SoC,用于数字地面电视和移动广播服务的无缝播放","authors":"K. Iwata, S. Mochizuki, Motoki Kimura, H. Ueda, Keisuke Matsumoto, Kazushi Akie, T. Shibayama, Hiroshi Hatae, Hiromi Watanabe","doi":"10.1109/ISCE.2010.5523720","DOIUrl":null,"url":null,"abstract":"A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.","PeriodicalId":403652,"journal":{"name":"IEEE International Symposium on Consumer Electronics (ISCE 2010)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An 80 mW dual video-codec SoC for seamless playback of digital terrestrial television and mobile broadcasting services\",\"authors\":\"K. Iwata, S. Mochizuki, Motoki Kimura, H. Ueda, Keisuke Matsumoto, Kazushi Akie, T. Shibayama, Hiroshi Hatae, Hiromi Watanabe\",\"doi\":\"10.1109/ISCE.2010.5523720\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.\",\"PeriodicalId\":403652,\"journal\":{\"name\":\"IEEE International Symposium on Consumer Electronics (ISCE 2010)\",\"volume\":\"28 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Consumer Electronics (ISCE 2010)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCE.2010.5523720\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Consumer Electronics (ISCE 2010)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCE.2010.5523720","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 80 mW dual video-codec SoC for seamless playback of digital terrestrial television and mobile broadcasting services
A mobile digital-terrestrial-television SoC with two multi-standard video codec is integrated on a 5.3×5.4 mm2 die in 45 nm CMOS. The dual video codec with dynamic frequency selection and advanced tile-based address translation consumes 80 mW in real-time playback of full-HD MPEG-2 and SD H.264 streams from 64 bits width low-power DDR-SDRAM at 1.1V.