超薄硅直接在绝缘体上(SDOI) mosfet在20nm栅极长度

2014 International Conference on High Performance Computing and Applications (ICHPCA) Pub Date : 2014-12-01 DOI:10.1109/ICHPCA.2014.7045357

S. K. Mohapatra, K. P. Pradhan, Prasanna Kumar Sahu, D. Singh, Sashmita Panda

{"title":"超薄硅直接在绝缘体上(SDOI) mosfet在20nm栅极长度","authors":"S. K. Mohapatra, K. P. Pradhan, Prasanna Kumar Sahu, D. Singh, Sashmita Panda","doi":"10.1109/ICHPCA.2014.7045357","DOIUrl":null,"url":null,"abstract":"This paper investigates on the scaling capability of nanoscale ultra-thin (UT) silicon directly on insulator (SDOI) single gate (SG) and double-gate (DG) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs). An experiment is done by numerical modelling for both NMOS and PMOS by using device simulator TCAD Sentaurus. Based on the model, we conduct an investigation on Short Channel Effects (SCEs) like drain induced barrier lowering (DIBL), threshold voltage (Vth) shifting between two devices. Two types (Single and Double gate) enhancement type MOSFET has been studied for nanoscale CMOS digital application.","PeriodicalId":197528,"journal":{"name":"2014 International Conference on High Performance Computing and Applications (ICHPCA)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Ultra-thin Si directly on insulator (SDOI) MOSFETs at 20 nm gate length\",\"authors\":\"S. K. Mohapatra, K. P. Pradhan, Prasanna Kumar Sahu, D. Singh, Sashmita Panda\",\"doi\":\"10.1109/ICHPCA.2014.7045357\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper investigates on the scaling capability of nanoscale ultra-thin (UT) silicon directly on insulator (SDOI) single gate (SG) and double-gate (DG) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs). An experiment is done by numerical modelling for both NMOS and PMOS by using device simulator TCAD Sentaurus. Based on the model, we conduct an investigation on Short Channel Effects (SCEs) like drain induced barrier lowering (DIBL), threshold voltage (Vth) shifting between two devices. Two types (Single and Double gate) enhancement type MOSFET has been studied for nanoscale CMOS digital application.\",\"PeriodicalId\":197528,\"journal\":{\"name\":\"2014 International Conference on High Performance Computing and Applications (ICHPCA)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 International Conference on High Performance Computing and Applications (ICHPCA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICHPCA.2014.7045357\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Conference on High Performance Computing and Applications (ICHPCA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICHPCA.2014.7045357","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文研究了纳米超薄(UT)硅直接绝缘体(SDOI)单门(SG)和双门(DG)金属氧化物半导体场效应晶体管(mosfet)的标度性能。利用TCAD Sentaurus对NMOS和PMOS进行了数值模拟实验。基于该模型，我们研究了短通道效应(sce)，如漏极诱导势垒降低(DIBL)，两个器件之间的阈值电压(Vth)移位。研究了两种类型(单栅极和双栅极)增强型MOSFET用于纳米级CMOS数字应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Ultra-thin Si directly on insulator (SDOI) MOSFETs at 20 nm gate length

This paper investigates on the scaling capability of nanoscale ultra-thin (UT) silicon directly on insulator (SDOI) single gate (SG) and double-gate (DG) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs). An experiment is done by numerical modelling for both NMOS and PMOS by using device simulator TCAD Sentaurus. Based on the model, we conduct an investigation on Short Channel Effects (SCEs) like drain induced barrier lowering (DIBL), threshold voltage (Vth) shifting between two devices. Two types (Single and Double gate) enhancement type MOSFET has been studied for nanoscale CMOS digital application.

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2014 International Conference on High Performance Computing and Applications (ICHPCA)

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