A. Keshavarzi, G. Schrom, Stephen Tang, Sean Ma, K. Bowman, S. Tyagi, Kevin Zhang, T. Linton, N. Hakim, S. Duvall, J. Brews, V. De
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Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage
Fluctuations in intrinsic linear V/sub T/, free of impact of parasitics, are measured for large arrays of NMOS and PMOS devices on a testchip in a 150nm logic technology. Local intrinsic /spl rho/V/sub T/, free of extrinsic process, length and width variations, is random, and worsens with reverse body bias. Although the traditional area-dependent component is dominant, a significant component of the fluctuations in small devices depends only on device width or length.
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