C. Radens, S. Kudelka, L. Nesbit, R. Malik, T. Dyer, C. Dubuc, T. Joseph, M. Seitz, L. Clevenger, N. Arnold, J. Mandelman, R. Divakaruni, D. Casarotto, D. Lea, V. C. Jaiprakash, J. Sim, J. Faltermeier, K. Low, J. Strane, S. Halle, Q. Ye, S. Bukofsky, U. Gruening, T. Schloesser, G. Bronner
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An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM
This paper describes a novel 6F/sup 2/ trench-capacitor DRAM with a trench-sidewall vertical-channel array transistor. The cell features a line/space pattern for the active area, single-sided buried-strap node contact, vertical transistor channel formed along the upper region of the trench capacitor, a device active area bounded by the isolation trench and capacitor collar, and a single bit contact per cell.
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