Ghil-geun Oh, Si-Jeong Kim, Kyeong-Ju Jin, Shin- Young Jung, Brandon Lee
{"title":"基于10nm制程高压扫描失效分析的导线RC影响","authors":"Ghil-geun Oh, Si-Jeong Kim, Kyeong-Ju Jin, Shin- Young Jung, Brandon Lee","doi":"10.1109/IPFA.2018.8452614","DOIUrl":null,"url":null,"abstract":"SCAN failure analysis that occurred only in the high voltage region was analyzed through in-circuit probing using laser voltage probing (LVP) technique in 10nm process. LVP results provided that high wire resistance of 4th metal layer had lead hold violation between launch and capture clock paths. This implies the importance of Back-End-Of-Line (BEOL) information that is monitored in mass production and design phase in high scaled process.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact of Wire RC Based on High Voltage SCAN Failure Analysis in 10nm Process\",\"authors\":\"Ghil-geun Oh, Si-Jeong Kim, Kyeong-Ju Jin, Shin- Young Jung, Brandon Lee\",\"doi\":\"10.1109/IPFA.2018.8452614\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"SCAN failure analysis that occurred only in the high voltage region was analyzed through in-circuit probing using laser voltage probing (LVP) technique in 10nm process. LVP results provided that high wire resistance of 4th metal layer had lead hold violation between launch and capture clock paths. This implies the importance of Back-End-Of-Line (BEOL) information that is monitored in mass production and design phase in high scaled process.\",\"PeriodicalId\":382811,\"journal\":{\"name\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2018.8452614\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2018.8452614","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Wire RC Based on High Voltage SCAN Failure Analysis in 10nm Process
SCAN failure analysis that occurred only in the high voltage region was analyzed through in-circuit probing using laser voltage probing (LVP) technique in 10nm process. LVP results provided that high wire resistance of 4th metal layer had lead hold violation between launch and capture clock paths. This implies the importance of Back-End-Of-Line (BEOL) information that is monitored in mass production and design phase in high scaled process.
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