600 V/100 A NPT-IGBT非自对准浅p井地层技术评价

M. Otsuki, S. Momota, M. Kirisawa, H. Wakimoto, Y. Seki
{"title":"600 V/100 A NPT-IGBT非自对准浅p井地层技术评价","authors":"M. Otsuki, S. Momota, M. Kirisawa, H. Wakimoto, Y. Seki","doi":"10.1109/ISPSD.2000.856812","DOIUrl":null,"url":null,"abstract":"Experimental results of planer gate IGBTs fabricated with newly developed a non-self-align shallow p-well formation technique are presented. The 600 V/100 A NPT-IGBT shows the on-state voltage drop of about 1.7 V, which is more than 0.4 V reduction compared to the conventional devices. The average short circuit withstand capability of about 30 /spl mu/sec was obtained without external current limiting functions.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques\",\"authors\":\"M. Otsuki, S. Momota, M. Kirisawa, H. Wakimoto, Y. Seki\",\"doi\":\"10.1109/ISPSD.2000.856812\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Experimental results of planer gate IGBTs fabricated with newly developed a non-self-align shallow p-well formation technique are presented. The 600 V/100 A NPT-IGBT shows the on-state voltage drop of about 1.7 V, which is more than 0.4 V reduction compared to the conventional devices. The average short circuit withstand capability of about 30 /spl mu/sec was obtained without external current limiting functions.\",\"PeriodicalId\":260241,\"journal\":{\"name\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"volume\":\"24 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2000.856812\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856812","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

介绍了采用新开发的非自对准浅p井成井技术制备平面栅igbt的实验结果。600 V/100 A NPT-IGBT的导通电压降约为1.7 V,与传统器件相比降低了0.4 V以上。在没有外部限流功能的情况下,平均抗短路能力约为30 /spl mu/sec。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques
Experimental results of planer gate IGBTs fabricated with newly developed a non-self-align shallow p-well formation technique are presented. The 600 V/100 A NPT-IGBT shows the on-state voltage drop of about 1.7 V, which is more than 0.4 V reduction compared to the conventional devices. The average short circuit withstand capability of about 30 /spl mu/sec was obtained without external current limiting functions.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Complementary LDMOS transistors for a CMOS/BiCMOS process Using "Adaptive resurf" to improve the SOA of LDMOS transistors Evaluation of 600 V/100 A NPT-IGBT with a non-self-align shallow p-well formation techniques A novel free wheeling diode for 1700 V IGBT module Low voltage CMOS compatible power MOSFET for on-chip DC/DC converters
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1