任意分数阶H型模拟分数电路

2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI:10.1109/ICASIC.2005.1611516

Zhou Jiliu, Pu Yifei, Yuan Xiao, Liao Ke

{"title":"任意分数阶H型模拟分数电路","authors":"Zhou Jiliu, Pu Yifei, Yuan Xiao, Liao Ke","doi":"10.1109/ICASIC.2005.1611516","DOIUrl":null,"url":null,"abstract":"In the first, the paper puts forward a frac12 order H type analog fractance circuit. In the second, it further puts forward any fractional order H type analog fractance circuit for any order fractional calculus. In the last, it is proved to performance correctly and efficiently by computer simulation and circuit analog. The result educing by the paper is the basis for further theoretic research and engineering implement to structure fractance circuit for any order fractional calculus","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Any fractional order H type analog fractance circuit\",\"authors\":\"Zhou Jiliu, Pu Yifei, Yuan Xiao, Liao Ke\",\"doi\":\"10.1109/ICASIC.2005.1611516\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the first, the paper puts forward a frac12 order H type analog fractance circuit. In the second, it further puts forward any fractional order H type analog fractance circuit for any order fractional calculus. In the last, it is proved to performance correctly and efficiently by computer simulation and circuit analog. The result educing by the paper is the basis for further theoretic research and engineering implement to structure fractance circuit for any order fractional calculus\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611516\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611516","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

本文首先提出了一种frac12阶H型模拟分数电路。其次，进一步提出了适用于任意阶分数阶微积分的任意阶阶H型模拟分数电路。最后，通过计算机仿真和电路模拟验证了该方法的正确性和有效性。本文的推导结果为进一步的理论研究和工程实现构建任意阶分数阶微积分的分数电路奠定了基础

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Any fractional order H type analog fractance circuit

In the first, the paper puts forward a frac12 order H type analog fractance circuit. In the second, it further puts forward any fractional order H type analog fractance circuit for any order fractional calculus. In the last, it is proved to performance correctly and efficiently by computer simulation and circuit analog. The result educing by the paper is the basis for further theoretic research and engineering implement to structure fractance circuit for any order fractional calculus

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2005 6th International Conference on ASIC

自引率

0.00%

发文量

期刊最新文献

A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers A VLSI architecture for motion compensation interpolation in H.264/AVC Transition traversal coverage estimation for symbolic model checking Power reduction in high-speed inter-chip data communications An optimization of VLSI architecture for DFE used in Ethernet