一个12b 5- 50ms /s 0.5- 1v电压可扩展的基于零交叉的流水线ADC

Sunghyuk Lee, A. Chandrakasan, Hae-Seung Lee
{"title":"一个12b 5- 50ms /s 0.5- 1v电压可扩展的基于零交叉的流水线ADC","authors":"Sunghyuk Lee, A. Chandrakasan, Hae-Seung Lee","doi":"10.1109/ESSCIRC.2011.6044980","DOIUrl":null,"url":null,"abstract":"A voltage scalable zero-crossing based (ZCB) pipelined ADC is built in 65nm GP (general purpose) CMOS process and LP (low power) CMOS process. The highly digital implementation characteristic of the zero-crossing based circuit technique enables energy efficient operation and supply voltage scaling. A unidirectional coarse-fine charge transfer scheme is developed to allow low-voltage operation as well as high speed and high resolution. At 1.0V(GP) / 1.2V(LP) nominal supply and 50MS/s, the ADC achieves 67.7dB(GP) / 68.1dB(LP) SNDR after calibration while dissipating 4.07mW(GP) / 4.93mW(LP), resulting in an FOM of 41.0fJ/step(GP) / 47.5fJ/step(LP). The supply voltage scalability is demonstrated down to 0.5V(GP) / 0.8V(LP) and improves the FOM to 28.0fJ/step(GP) / 37.8fJ/step(LP), while maintaining higher than 66dB SNDR.","PeriodicalId":239979,"journal":{"name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC\",\"authors\":\"Sunghyuk Lee, A. Chandrakasan, Hae-Seung Lee\",\"doi\":\"10.1109/ESSCIRC.2011.6044980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A voltage scalable zero-crossing based (ZCB) pipelined ADC is built in 65nm GP (general purpose) CMOS process and LP (low power) CMOS process. The highly digital implementation characteristic of the zero-crossing based circuit technique enables energy efficient operation and supply voltage scaling. A unidirectional coarse-fine charge transfer scheme is developed to allow low-voltage operation as well as high speed and high resolution. At 1.0V(GP) / 1.2V(LP) nominal supply and 50MS/s, the ADC achieves 67.7dB(GP) / 68.1dB(LP) SNDR after calibration while dissipating 4.07mW(GP) / 4.93mW(LP), resulting in an FOM of 41.0fJ/step(GP) / 47.5fJ/step(LP). The supply voltage scalability is demonstrated down to 0.5V(GP) / 0.8V(LP) and improves the FOM to 28.0fJ/step(GP) / 37.8fJ/step(LP), while maintaining higher than 66dB SNDR.\",\"PeriodicalId\":239979,\"journal\":{\"name\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-10-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2011.6044980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2011.6044980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

采用65nm GP(通用)CMOS工艺和LP(低功耗)CMOS工艺,构建了电压可扩展的基于过零(ZCB)的流水线ADC。基于过零电路技术的高度数字化实现特性使节能操作和电源电压缩放成为可能。为了实现低电压、高速度和高分辨率的工作,提出了一种单向粗-细电荷转移方案。在1.0V(GP) / 1.2V(LP)标称电源和50MS/s下,ADC在校准后实现67.7dB(GP) / 68.1dB(LP) SNDR,同时耗散4.07mW(GP) / 4.93mW(LP),导致FOM为41.0fJ/步长(GP) / 47.5fJ/步长(LP)。电源电压可扩展性低至0.5V(GP) / 0.8V(LP),并将FOM提高至28.0fJ/step(GP) / 37.8fJ/step(LP),同时保持高于66dB的SNDR。
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A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC
A voltage scalable zero-crossing based (ZCB) pipelined ADC is built in 65nm GP (general purpose) CMOS process and LP (low power) CMOS process. The highly digital implementation characteristic of the zero-crossing based circuit technique enables energy efficient operation and supply voltage scaling. A unidirectional coarse-fine charge transfer scheme is developed to allow low-voltage operation as well as high speed and high resolution. At 1.0V(GP) / 1.2V(LP) nominal supply and 50MS/s, the ADC achieves 67.7dB(GP) / 68.1dB(LP) SNDR after calibration while dissipating 4.07mW(GP) / 4.93mW(LP), resulting in an FOM of 41.0fJ/step(GP) / 47.5fJ/step(LP). The supply voltage scalability is demonstrated down to 0.5V(GP) / 0.8V(LP) and improves the FOM to 28.0fJ/step(GP) / 37.8fJ/step(LP), while maintaining higher than 66dB SNDR.
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