{"title":"流水线GF算术电路的形式化设计及其在密码处理器中的应用","authors":"Rei Ueno, Yukihiro Sugawara, N. Homma, T. Aoki","doi":"10.1109/ISMVL.2016.25","DOIUrl":null,"url":null,"abstract":"This study presents a formal approach to designing pipelined arithmetic circuits over Galois fields (GFs). The proposed method extends a graph-based circuit description known as a Galois-field arithmetic circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.","PeriodicalId":246194,"journal":{"name":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","volume":"327 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors\",\"authors\":\"Rei Ueno, Yukihiro Sugawara, N. Homma, T. Aoki\",\"doi\":\"10.1109/ISMVL.2016.25\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This study presents a formal approach to designing pipelined arithmetic circuits over Galois fields (GFs). The proposed method extends a graph-based circuit description known as a Galois-field arithmetic circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.\",\"PeriodicalId\":246194,\"journal\":{\"name\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":\"327 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2016.25\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 46th International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2016.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors
This study presents a formal approach to designing pipelined arithmetic circuits over Galois fields (GFs). The proposed method extends a graph-based circuit description known as a Galois-field arithmetic circuit graph (GF-ACG) to Linear-time Temporal Logic (LTL) in order to represent the timing property of pipelined circuits. We first present the extension of GF-ACG and its formal verification using computer algebra. We then demonstrate the efficiency of the proposed method through an experimental design of a lightweight cryptographic processor. In particular, we design a tamper-resistant datapath with threshold Implementation (TI) based on pipelining and multi-party computation. The proposed method can verify the processor within 1 h, whereas conventional methods would fail.