{"title":"实时高清电视视频解码器","authors":"N. Ling, N. Wang","doi":"10.1109/SIPS.2001.957354","DOIUrl":null,"url":null,"abstract":"We present an architecture for real-time digital HDTV video decoding. Our technique is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces the memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1920/spl times/1080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbit/s.","PeriodicalId":246898,"journal":{"name":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","volume":"11 1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A real-time HDTV video decoder\",\"authors\":\"N. Ling, N. Wang\",\"doi\":\"10.1109/SIPS.2001.957354\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present an architecture for real-time digital HDTV video decoding. Our technique is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces the memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1920/spl times/1080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbit/s.\",\"PeriodicalId\":246898,\"journal\":{\"name\":\"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)\",\"volume\":\"11 1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.2001.957354\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 IEEE Workshop on Signal Processing Systems. SiPS 2001. Design and Implementation (Cat. No.01TH8578)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2001.957354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We present an architecture for real-time digital HDTV video decoding. Our technique is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces the memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1920/spl times/1080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbit/s.