Design of delay-verifiable combinational logic by adding extra inputs

Correct operation of logic circuits requires not only the functional correctness, but also the correctness of temporal behavior. This paper deals with the problem of delay testability of two-level circuits through adding extra inputs. A design of delay-verifiable combinational logic by adding extra inputs is proposed, and a synthesis procedure is given. Experimental results show that the hardware overhead is about 1/3 of that of the methods proposed previously (1987, 1991), which aim at robust testable or VNR testable circuits. In fact, it is good enough to guarantee delay verifiability to satisfy the requirement of temporal correctness.