考虑串扰噪声的互连性能角

Ravikishore Gandikota, D. Blaauw, D. Sylvester
{"title":"考虑串扰噪声的互连性能角","authors":"Ravikishore Gandikota, D. Blaauw, D. Sylvester","doi":"10.1109/ICCD.2009.5413148","DOIUrl":null,"url":null,"abstract":"Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not switching and no coupling-noise is injected on the victim net. In this paper, we first show that the interconnect corners obtained under such assumptions could in reality be much different from the true interconnect corner and could therefore result in optimistic delay analysis, particularly for fast-path analysis performed to check hold time violations. We also show that in some cases, the interconnect corner may not lie at an extreme point of the process variation range. In this work, we use the Elmore delay metric to efficiently search for the correct interconnect corner of the victim stage considering delay noise. We then show experimental results to verify the effectiveness of our proposed approach and demonstrate that the traditional approaches of computing the interconnect corners could lead to errors of up to 60% on a net by net basis.","PeriodicalId":256908,"journal":{"name":"2009 IEEE International Conference on Computer Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Interconnect performance corners considering crosstalk noise\",\"authors\":\"Ravikishore Gandikota, D. Blaauw, D. Sylvester\",\"doi\":\"10.1109/ICCD.2009.5413148\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not switching and no coupling-noise is injected on the victim net. In this paper, we first show that the interconnect corners obtained under such assumptions could in reality be much different from the true interconnect corner and could therefore result in optimistic delay analysis, particularly for fast-path analysis performed to check hold time violations. We also show that in some cases, the interconnect corner may not lie at an extreme point of the process variation range. In this work, we use the Elmore delay metric to efficiently search for the correct interconnect corner of the victim stage considering delay noise. We then show experimental results to verify the effectiveness of our proposed approach and demonstrate that the traditional approaches of computing the interconnect corners could lead to errors of up to 60% on a net by net basis.\",\"PeriodicalId\":256908,\"journal\":{\"name\":\"2009 IEEE International Conference on Computer Design\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Conference on Computer Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCD.2009.5413148\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Conference on Computer Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCD.2009.5413148","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

工艺引起的互连电容和电阻的变化导致了互连延迟的显著不确定性。在这项工作中,我们提出了一种考虑入侵源同时切换引起的耦合噪声的互连角点计算新方法。在先前的方法中,互连角的计算是在假设攻击网没有切换和没有耦合噪声注入到受害网的情况下进行的。在本文中,我们首先表明,在这些假设下获得的互连角实际上可能与真实互连角有很大不同,因此可能导致乐观延迟分析,特别是用于检查保持时间违规的快速路径分析。我们还表明,在某些情况下,互连角可能不在工艺变化范围的极端点上。在这项工作中,我们使用Elmore延迟度量在考虑延迟噪声的情况下有效地搜索受害级的正确互连角。然后,我们展示了实验结果来验证我们提出的方法的有效性,并证明传统的互连角点计算方法在逐净的基础上可能导致高达60%的误差。
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Interconnect performance corners considering crosstalk noise
Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not switching and no coupling-noise is injected on the victim net. In this paper, we first show that the interconnect corners obtained under such assumptions could in reality be much different from the true interconnect corner and could therefore result in optimistic delay analysis, particularly for fast-path analysis performed to check hold time violations. We also show that in some cases, the interconnect corner may not lie at an extreme point of the process variation range. In this work, we use the Elmore delay metric to efficiently search for the correct interconnect corner of the victim stage considering delay noise. We then show experimental results to verify the effectiveness of our proposed approach and demonstrate that the traditional approaches of computing the interconnect corners could lead to errors of up to 60% on a net by net basis.
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