Systolic Variable Length Architecture for Discrete Fourier Transform in Long Term Evolution

A novel design for the implementation of the 2M x 3P x 5Q point Discrete Fourier Transform (DFT) computation for Single Carrier-Frequency Division Multiple Access (SC-FDMA) systems as defined by the Long Term Evolution standard is proposed. The design is based on the Systolic Architecture. The decomposition of the DFT computation into factors of two, three, four and five is implemented by a recursive invocation of the Cooley-Tukey Algorithm, with the individual DFTs within each Cooley Tukey iteration implemented using the Winograd Fourier Transform Algorithm (WFTA). The proposed architecture is superior to the Intellectual Property (IP) cores proposed by Xilinx R in that the clock frequency requirements are reduced by a factor of up to 5.2 (approx), resulting in significant savings in the total power dissipation.