S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall
{"title":"在0.25 /spl mu/m的块体CMOS中实现单片、流水线、复杂的一维快速傅里叶变换","authors":"S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall","doi":"10.1109/ASAP.2002.1030732","DOIUrl":null,"url":null,"abstract":"The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS\",\"authors\":\"S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall\",\"doi\":\"10.1109/ASAP.2002.1030732\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.\",\"PeriodicalId\":424082,\"journal\":{\"name\":\"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-07-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.2002.1030732\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2002.1030732","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS
The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.