在0.25 /spl mu/m的块体CMOS中实现单片、流水线、复杂的一维快速傅里叶变换

S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall
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引用次数: 10

摘要

梅奥基金会特殊用途处理器开发小组(Mayo)开发了一种新型的快速傅立叶变换(FFT) ASIC,设计用于16位复杂(16位实、16位虚)样本。基数为2的FFT处理器可以根据用户的选择,在2点和4096点之间执行任意2次幂大小的变换。FFT处理器完全包含在单个10mm × 10mm的芯片上,采用0.25 /spl mu/m批量CMOS技术实现,包括用于存储所有中间计算的分布式寄存器组,以及用于存储用户可编程正弦和余弦系数的静态RAM (SRAM)。设计最大的灵活性,梅奥FFT处理器包括冗余计算模块,用户可编程的变换长度;每个计算模块的独立、用户可编程的正弦和余弦系数存储SRAM;溢出检测和校正电路(在每个计算模块中以用户可选择的操作数缩放的形式),5伏容忍3.3伏I/O;还有一个命令驱动的界面。
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Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS
The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
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Low power memory design Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS Instruction stream mutation for non-deterministic processors New results on array contraction [memory optimization] Predictable instruction caching for media processors
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