Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030700
M. Manjunathaiah, G. Megson
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align data flow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.
{"title":"Compositional technique for synthesising multi-phase regular arrays","authors":"M. Manjunathaiah, G. Megson","doi":"10.1109/ASAP.2002.1030700","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030700","url":null,"abstract":"We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align data flow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030707
Lin Yuan, G. Qu
We consider two of the most important design issues for distributed sensor networks in the battlefield: security for communication in such hostile terrain; and energy efficiency because of the battery's limited capacity and the impracticality of recharging. Communication security is normally provided by encryption, i.e. data are encrypted before transmission and are decrypted first on reception. We exploit the secure sensor network design space for energy efficiency by investigating different microprocessors coupled with various public key algorithms. We propose a power control mechanism for sensors to operate in an energy-efficient fashion using the newly developed dynamical voltage scaling (DVS) technique. In particular we consider multiple voltage processors and insert additional information into the communication channel to guide the selection of proper voltages for data decryption/encryption and processing in order to reduce the total computational energy consumption. We experiment several encryption standards on a broad range of embedded processors and simulate the behavior of the sensor network to show that the sensor's lifetime can be extended substantially.
{"title":"Design space exploration for energy-efficient secure sensor network","authors":"Lin Yuan, G. Qu","doi":"10.1109/ASAP.2002.1030707","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030707","url":null,"abstract":"We consider two of the most important design issues for distributed sensor networks in the battlefield: security for communication in such hostile terrain; and energy efficiency because of the battery's limited capacity and the impracticality of recharging. Communication security is normally provided by encryption, i.e. data are encrypted before transmission and are decrypted first on reception. We exploit the secure sensor network design space for energy efficiency by investigating different microprocessors coupled with various public key algorithms. We propose a power control mechanism for sensors to operate in an energy-efficient fashion using the newly developed dynamical voltage scaling (DVS) technique. In particular we consider multiple voltage processors and insert additional information into the communication channel to guide the selection of proper voltages for data decryption/encryption and processing in order to reduce the total computational energy consumption. We experiment several encryption standards on a broad range of embedded processors and simulate the behavior of the sensor network to show that the sensor's lifetime can be extended substantially.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126160537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030713
J. Irwin, D. May, H. Muller, D. Page
The determinism of instruction cache performance can be considered a major problem in multimedia devices which hope to maximise their quality of service. If instructions are evicted from the cache by competing blocks of code, the running application will take significantly longer to execute than if the instructions were present. Since it is difficult to predict when this interference will occur the performance of the algorithm at a given point in time is unclear We propose the use of an automatically configured partitioned cache to protect regions of the application code from each other and hence minimise interference. As well as being specialised to the purpose of providing predictable performance, this cache can be specialised to the application being run, rather than for the average case, using simple compiler algorithms.
{"title":"Predictable instruction caching for media processors","authors":"J. Irwin, D. May, H. Muller, D. Page","doi":"10.1109/ASAP.2002.1030713","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030713","url":null,"abstract":"The determinism of instruction cache performance can be considered a major problem in multimedia devices which hope to maximise their quality of service. If instructions are evicted from the cache by competing blocks of code, the running application will take significantly longer to execute than if the instructions were present. Since it is difficult to predict when this interference will occur the performance of the algorithm at a given point in time is unclear We propose the use of an automatically configured partitioned cache to protect regions of the application code from each other and hence minimise interference. As well as being specialised to the purpose of providing predictable performance, this cache can be specialised to the application being run, rather than for the average case, using simple compiler algorithms.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030726
Chih-Chung Lu, S. Tseng
This paper proposed a method of integrating the AES encrypter and the AES decrypter into a full functional AES crypto-engine. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv)SubBytes module and (Inv)Mixcolumns module, etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart cards, PDAs, and mobile phones, etc.
{"title":"Integrated design of AES (Advanced Encryption Standard) encrypter and decrypter","authors":"Chih-Chung Lu, S. Tseng","doi":"10.1109/ASAP.2002.1030726","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030726","url":null,"abstract":"This paper proposed a method of integrating the AES encrypter and the AES decrypter into a full functional AES crypto-engine. This method can make it a very low-complexity architecture, especially in saving the hardware resource in implementing the AES (Inv)SubBytes module and (Inv)Mixcolumns module, etc. Most designed modules can be used for both AES encryption and decryption. Besides, the architecture can still deliver a high data rate in both encryption/decryption operations. The proposed architecture is suited for hardware-critical applications, such as smart cards, PDAs, and mobile phones, etc.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132501055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030733
R. Chamberlain, M. Franklin, P. Krishnamurthy
This paper considers a class of embedded signal processing applications. To achieve real-time performance these applications must be executed on a parallel processor. The paper focuses on the multiring optical interconnection network used in the system and specifically on the performance gains associated with utilizing the bandwidth reconfiguration capabilities associated with the network. The network is capable of being reconfigured to provide designated bandwidths to different source-destination connections both across rings and within a ring. The applications each consist of a sequence of alternating communication and computation phases. The sequence continues until execution of the application is complete. The effect of reconfiguration on application performance is explored using simulation techniques. The results indicate that substantial performance gains (speedups of 2 or more) can be achieved for this application class.
{"title":"Optical network reconfiguration for signal processing applications","authors":"R. Chamberlain, M. Franklin, P. Krishnamurthy","doi":"10.1109/ASAP.2002.1030733","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030733","url":null,"abstract":"This paper considers a class of embedded signal processing applications. To achieve real-time performance these applications must be executed on a parallel processor. The paper focuses on the multiring optical interconnection network used in the system and specifically on the performance gains associated with utilizing the bandwidth reconfiguration capabilities associated with the network. The network is capable of being reconfigured to provide designated bandwidths to different source-destination connections both across rings and within a ring. The applications each consist of a sequence of alternating communication and computation phases. The sequence continues until execution of the application is complete. The effect of reconfiguration on application performance is explored using simulation techniques. The results indicate that substantial performance gains (speedups of 2 or more) can be achieved for this application class.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132357492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030738
M. DeVore, R. Chamberlain, G. Engel, J. O’Sullivan, M. Franklin
The implementation of computational systems to perform challenging operations often involves balancing the performance specification, system throughput, and available system resources. For problems of automatic target recognition (ATR), these three quantities of interest are the probability of classification error, the rate at which regions of interest are processed, and the capabilities of the underlying hardware (which is a function of the available computational resources and available power). An understanding of the inter-relationships between these factors can be an aid in making informed choices while exploring competing design possibilities. Combining characterizations of ATR performance, which yield probability of classification error as a function of target model complexity, with analytical models of computational performance, which yield throughput as a function of target model complexity and available resources, we can form a set of parametric curves which relate the quality of the results to the resources consumed.
{"title":"Tradeoffs between quality of results and resource consumption in a recognition system","authors":"M. DeVore, R. Chamberlain, G. Engel, J. O’Sullivan, M. Franklin","doi":"10.1109/ASAP.2002.1030738","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030738","url":null,"abstract":"The implementation of computational systems to perform challenging operations often involves balancing the performance specification, system throughput, and available system resources. For problems of automatic target recognition (ATR), these three quantities of interest are the probability of classification error, the rate at which regions of interest are processed, and the capabilities of the underlying hardware (which is a function of the available computational resources and available power). An understanding of the inter-relationships between these factors can be an aid in making informed choices while exploring competing design possibilities. Combining characterizations of ATR performance, which yield probability of classification error as a function of target model complexity, with analytical models of computational performance, which yield throughput as a function of target model complexity and available resources, we can form a set of parametric curves which relate the quality of the results to the resources consumed.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133359006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030704
Wen-Tsong Shiue
In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of storage bandwidth optimization (SBO) techniques to simplify the conflict graph and (ii) use of memory exploration techniques to determine the best memory configuration (number of modules, size and number of ports per module) with the minimum area if the energy and timing are bounded or with the minimum energy/timing if the area is bounded. Here the simplest conflict graph implies more possibilities for the arrays assigned to the same module without the penalty in an increase of the number of ports for each module. Our benchmark shows that the heuristic algorithm is very efficient to decide the best memory configuration for the system constraints (timing, area, or energy). In addition, the CACTI tool (Premkishore Shivakumar and N.P. Jouppi, 2001) is modified to estimate the timing, area, and energy for each module in different CMOS technologies (0.8 /spl mu/m, 0.35 /spl mu/m, and 0.18 /spl mu/m). Furthermore, we consider the lifetime for arrays; this results in significant reduction in timing, area, and energy for the arrays executed in different cycles sharing the same memory module.
{"title":"Low power memory design","authors":"Wen-Tsong Shiue","doi":"10.1109/ASAP.2002.1030704","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030704","url":null,"abstract":"In this paper, we present a novel design procedure for multi-module, multi-port memory design that satisfies area and/or energy/timing constraints. Our procedure consists of (i) use of storage bandwidth optimization (SBO) techniques to simplify the conflict graph and (ii) use of memory exploration techniques to determine the best memory configuration (number of modules, size and number of ports per module) with the minimum area if the energy and timing are bounded or with the minimum energy/timing if the area is bounded. Here the simplest conflict graph implies more possibilities for the arrays assigned to the same module without the penalty in an increase of the number of ports for each module. Our benchmark shows that the heuristic algorithm is very efficient to decide the best memory configuration for the system constraints (timing, area, or energy). In addition, the CACTI tool (Premkishore Shivakumar and N.P. Jouppi, 2001) is modified to estimate the timing, area, and energy for each module in different CMOS technologies (0.8 /spl mu/m, 0.35 /spl mu/m, and 0.18 /spl mu/m). Furthermore, we consider the lifetime for arrays; this results in significant reduction in timing, area, and energy for the arrays executed in different cycles sharing the same memory module.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"32 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114270085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030732
S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall
The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.
{"title":"Implementation of a single chip, pipelined, complex, one-dimensional fast Fourier transform in 0.25 /spl mu/m bulk CMOS","authors":"S. Currie, P. Schumacher, B. Gilbert, E. Swartzlander, B. Randall","doi":"10.1109/ASAP.2002.1030732","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030732","url":null,"abstract":"The Mayo Foundation Special Purpose Processor Development Group (Mayo) has developed a novel fast Fourier transform (FFT) ASIC designed to operate on 16-bit complex (16-bit real, 16-bit imaginary) samples. The radix-2 FFT processor performs any power-of-two-sized transform between 2-point and 4096-point, as selected by the user. The FFT processor is wholly contained on a single 10 mm by 10 mm die implemented in 0.25 /spl mu/m bulk CMOS technology, including distributed register banks for storing all intermediate calculations, and static RAM (SRAM) for storing user programmable sine and cosine coefficients. Designed for maximum flexibility, the Mayo FFT processor includes redundant computation modules, user programmable transform length; individual, user programmable sine and cosine coefficient-storing SRAM for each of the computation modules; overflow detection and correction circuitry (in the form of user-selectable operand scaling within each computation module), 5-volt tolerant 3.3-volt I/O; and a command driven interface.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114435571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030736
T. Liao, Ta-Yin Hu
With the advancement of intelligent transportation systems (ITS), the current and future emergency medical services (EMS) systems are characterized by real-time response, specialization, and decentralization. In order to provide real-time response of medical services, several components are essential, such as dispatching, routing, emergency facilities, and patients medical history. This paper proposes a CORBA (common object request broker architecture)-based GIS-T (geographic information systems for transportation) framework for the dispatching and assignment of medical vehicles for emergency services via wireless communication. The framework combines distributed object computing, GIS-T, and transportation models in a single system, thus provides flexibility and interoperability among existing medical service systems. The framework utilizes the concept of distributed systems and capabilities of CORBA to design objects and dynamically updated medical facilities information in order to provide ambulances with up-to-date information. A real roadway network is used in the numerical experiments to illustrate dynamic aspects of the proposed system.
{"title":"A CORBA-based GIS-T for ambulance assignment","authors":"T. Liao, Ta-Yin Hu","doi":"10.1109/ASAP.2002.1030736","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030736","url":null,"abstract":"With the advancement of intelligent transportation systems (ITS), the current and future emergency medical services (EMS) systems are characterized by real-time response, specialization, and decentralization. In order to provide real-time response of medical services, several components are essential, such as dispatching, routing, emergency facilities, and patients medical history. This paper proposes a CORBA (common object request broker architecture)-based GIS-T (geographic information systems for transportation) framework for the dispatching and assignment of medical vehicles for emergency services via wireless communication. The framework combines distributed object computing, GIS-T, and transportation models in a single system, thus provides flexibility and interoperability among existing medical service systems. The framework utilizes the concept of distributed systems and capabilities of CORBA to design objects and dynamically updated medical facilities information in order to provide ambulances with up-to-date information. A real roadway network is used in the numerical experiments to illustrate dynamic aspects of the proposed system.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-07-17DOI: 10.1109/ASAP.2002.1030737
D. Cachera, T. Risset
We describe a method for the formal determination of signal bit width in fixed point VLSI implementations of signal processing algorithms containing loop nests. The main contribution of this paper is the use of results of the (max, +) algebraic theory to find the integral bit width of algorithms containing loop nests whose bound parameters are not statically known. Combined with recent results on fractional bit width determination, this can be used for 1-dimensional systolic-like arrays implementing linear signal processing algorithms. Although this technique is presented in the context of a specific high level design methodology (based on systems of affine recurrence equations), it can be used in many high level design environments.
{"title":"Advances in bit width selection methodology","authors":"D. Cachera, T. Risset","doi":"10.1109/ASAP.2002.1030737","DOIUrl":"https://doi.org/10.1109/ASAP.2002.1030737","url":null,"abstract":"We describe a method for the formal determination of signal bit width in fixed point VLSI implementations of signal processing algorithms containing loop nests. The main contribution of this paper is the use of results of the (max, +) algebraic theory to find the integral bit width of algorithms containing loop nests whose bound parameters are not statically known. Combined with recent results on fractional bit width determination, this can be used for 1-dimensional systolic-like arrays implementing linear signal processing algorithms. Although this technique is presented in the context of a specific high level design methodology (based on systems of affine recurrence equations), it can be used in many high level design environments.","PeriodicalId":424082,"journal":{"name":"Proceedings IEEE International Conference on Application- Specific Systems, Architectures, and Processors","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：