{"title":"MUSE:晶圆级收缩DSP","authors":"D. L. Allen, A. Anderson, C. Rader, C. Woodward","doi":"10.1109/ICWSI.1990.63879","DOIUrl":null,"url":null,"abstract":"MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 mu m CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4\" by 4\" silicon substrate.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"MUSE: a wafer-scale systolic DSP\",\"authors\":\"D. L. Allen, A. Anderson, C. Rader, C. Woodward\",\"doi\":\"10.1109/ICWSI.1990.63879\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 mu m CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4\\\" by 4\\\" silicon substrate.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63879\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63879","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
MUSE (Matrix Update Systolic Experiment) is a special-purpose digital signal processor being implemented using restructurable VLSI. It will consist of 5 million working transistors on a single wafer-scale integrated circuit. MUSE is a wafer-scale systolic array designed to operate at the continuous rate of 285 million rotations per second. It will enable space-based radar systems to perform real-time adaptive nulling on up to 63 jammers with nulls of 50 dB. The rotator cell has been fabricated in 2 mu m CMOS; a small testbed for 4 PEs has been built and operates at specification. Design for the wafer-scale interconnect is in progress. MUSE is a 1.7 Billion Real Operations per Second system which fits on a single 4" by 4" silicon substrate.<>
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