{"title":"反垫阵列对PCB电网面积填充电感的影响","authors":"Qixuan Sun, S. Bai, J. Drewniak, E. Li","doi":"10.1109/EDAPS.2017.8277012","DOIUrl":null,"url":null,"abstract":"A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The influence of anti-pad array on the inductance of PCB power net area fill\",\"authors\":\"Qixuan Sun, S. Bai, J. Drewniak, E. Li\",\"doi\":\"10.1109/EDAPS.2017.8277012\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.\",\"PeriodicalId\":329279,\"journal\":{\"name\":\"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2017.8277012\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2017.8277012","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The influence of anti-pad array on the inductance of PCB power net area fill
A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.
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