{"title":"采用90纳米技术的10位电流转向DAC","authors":"Tyler Moody, S. Ren, R. Ewing","doi":"10.1109/NAECON.2014.7045832","DOIUrl":null,"url":null,"abstract":"The design of a high speed current steering DAC using 90 nm CMOS technology is presented. The resolution for this design is 10 bits, segmented into 6 thermometer encoded current cells and 4 binary weighted current cells. Thermometer encoding is used instead of binary coded decimal to reduce glitches since only one bit changes at a time. The design methodology of the sub-components such as current cell, thermometer encoder, and bias circuits are discussed. The simulation results show the input bandwidth of the DAC is 250 MHz.","PeriodicalId":318539,"journal":{"name":"NAECON 2014 - IEEE National Aerospace and Electronics Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"10 bit current steering DAC in 90 nm technology\",\"authors\":\"Tyler Moody, S. Ren, R. Ewing\",\"doi\":\"10.1109/NAECON.2014.7045832\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The design of a high speed current steering DAC using 90 nm CMOS technology is presented. The resolution for this design is 10 bits, segmented into 6 thermometer encoded current cells and 4 binary weighted current cells. Thermometer encoding is used instead of binary coded decimal to reduce glitches since only one bit changes at a time. The design methodology of the sub-components such as current cell, thermometer encoder, and bias circuits are discussed. The simulation results show the input bandwidth of the DAC is 250 MHz.\",\"PeriodicalId\":318539,\"journal\":{\"name\":\"NAECON 2014 - IEEE National Aerospace and Electronics Conference\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-06-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"NAECON 2014 - IEEE National Aerospace and Electronics Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NAECON.2014.7045832\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"NAECON 2014 - IEEE National Aerospace and Electronics Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAECON.2014.7045832","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design of a high speed current steering DAC using 90 nm CMOS technology is presented. The resolution for this design is 10 bits, segmented into 6 thermometer encoded current cells and 4 binary weighted current cells. Thermometer encoding is used instead of binary coded decimal to reduce glitches since only one bit changes at a time. The design methodology of the sub-components such as current cell, thermometer encoder, and bias circuits are discussed. The simulation results show the input bandwidth of the DAC is 250 MHz.
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