Smart chip, system and data center enabled by advanced flexible cooling resources

The management of energy as a key resource will be a requirement from an economic and sustainability standpoint for the future computing utility. In addition to billions of computing devices, the miniaturization of semiconductor technologies will push the current power density of the microprocessor core over 200 W/cm/sup 2/ resulting in the use of active heat removal techniques. In order to facilitate thermal management of such high power density sources, and to enable energy efficiency, measured application of active cooling resources will be required. State of the art application of heat removal technologies, applied based on maximum heat load and managed with a lack of knowledge of the overall system requirements, will not suffice. Balanced use of energy to actively remove heat from the source, together with management of heat dissipated from the source, will be necessary to reduce the total cost of ownership of information technology equipment and services. Indeed, based on the current trajectory in chip design, future chips will have the flexibility to scale power, albeit at some performance penalty. This variability in heat generation must be utilized to enable balanced chip performance based on the most efficient provisioning of cooling resources. To enable "right" provisioning of cooling resources, flexibility must be devised at all levels of the heat removal stack - chip, system and data center. The ability to change the temperature and coolant mass flow is the required high level abstraction in this heat removal stack. With these underlying flexibilities in heat generation and heat removal, one can overlay a low-cost sensing network and create a control system that can modulate the cooling resources and work "hand in hand" with a power scheduling mechanism to create an energy aware global computing utility.