An 1.4Gbps/ch LVDS Receiver with Jitter-Boundary-Based Digital De-skew Algorithm

This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as symmetric one. In addition, it lowers the accumulated jitter through the delay adjustment of data path. Test chip was fabricated with 0.25 mum 5-metal CMOS technology. When 87.9 ps rms jitter is applied with the data rate of 1.4 Gbps as an input data, it recovers data with the BER of less than 10-11. When the transition maximized pattern is applied, the receiver dissipates 381 mW.