Design and analysis of phase locked loop in 90nm CMOS

Power has become one of the most important concerns in design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. Power consumption has become a bottleneck in microprocessor design. In an effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. Lowering the supply voltage, however, also reduces the performance of the circuit, which is usually unacceptable. Phase Lock Loop (PLL) is an important analog circuit used in various communication applications such as frequency synthesizer, radio, computer, clock generation, clock recovery, etc. Since all these applications are operating at different frequency, satisfying design constraints for PLL with respect to type of PLL operating frequency, Bandwidth, Settling time and other parameters is an critical and time consuming issue. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop (PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal circuit as its architecture involves both digital and analog signal processing units. The present work is implemented in Cadence 90nm CMOS technology.