基于片上系统的远程医疗安全现场可编程门阵列

N. M. Thamrin, Illiasaak Ahmad, M. Khalil Hani
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引用次数: 6

摘要

在远程医疗中,机密信息通过不安全的通道从一方传递到另一方。本文提出了一种基于现场可编程门阵列(FPGA)的远程医疗系统数据保护方法——mySECURE II。本文提出了两种基于片上系统(SoC)的加密方案:混合加密方案和基于Rivest-Shamir-Adleman (RSA)的数字签名方案。重点开发了128位高级加密标准(AES)子系统、2048位RSA加密子系统和安全哈希算法(SHA-1)加密子系统。在AES加密和RSA加密子系统中,这些密码系统的强度依赖于密钥。因此,设计了一种混合随机数生成器(RNG)来提供片上密钥生成操作。采用软硬件协同设计技术设计了加密SOC。硬件子系统设计在Altera Stratix 1S40F780C5 FPGA开发板上实现,并与Nios II处理器集成,形成了可编程芯片系统(System of Programmable Chip, SoPC)环境下的完整密码系统。软件设计包括硬件子系统通信的设备驱动程序的开发,以及加密服务提供程序(CSP)在主机上作为应用程序编程接口(API)的实现。因此,已经开发了一个原型来测试加密硬件子系统的功能以及CSP的可用性。
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A secure field programmable gate array based System-on-Chip for Telemedicine application
In Telemedicine, confidential information is transferred through an unsecure channel from one party to another. In this paper, a field programmable gate array (FPGA) based approach to protect the data in the Telemedicine system, the mySECURE II is developed. There are two security schemes on a crypto System-on-Chip (SoC) proposed in this paper namely hybrid encryption scheme and Rivest-Shamir-Adleman (RSA) based digital signature scheme. It focuses on the development of 128-bit Advanced Encryption Standard (AES) subsystem, 2048-bit RSA crypto subsystem and Secure Hash Algorithm (SHA-1) crypto subsystem. In AES encryption and RSA crypto subsystems, the strength of these cryptosystems relies on keys. Therefore, a hybrid random number generator (RNG) is designed to provide on-chip key generation operation in this work. The crypto SOC is designed using hardware-software co-design technique. The hardware subsystems design are implemented on Altera Stratix 1S40F780C5 FPGA development board and integrated with Nios II processor to form a complete cryptosystem in System of Programmable Chip (SoPC) environment. The software design consists of the development of device drivers for hardware subsystem communication, and implementation of Cryptographic Service Provider (CSP), serves as the Application Programming Interface (API) in host PC. As a result, a prototype has been developed to test the functionality of the crypto hardware subsystem as well as the usability of the CSP.
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