{"title":"通过仿真进行可靠性分析的构件建模","authors":"B. Alizadeh, Z. Navabi","doi":"10.1109/VIUF.1997.623954","DOIUrl":null,"url":null,"abstract":"This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov model.","PeriodicalId":212876,"journal":{"name":"Proceedings VHDL International Users' Forum. Fall Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Component modeling for reliability analysis by simulation\",\"authors\":\"B. Alizadeh, Z. Navabi\",\"doi\":\"10.1109/VIUF.1997.623954\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov model.\",\"PeriodicalId\":212876,\"journal\":{\"name\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-10-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings VHDL International Users' Forum. Fall Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VIUF.1997.623954\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings VHDL International Users' Forum. Fall Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VIUF.1997.623954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Component modeling for reliability analysis by simulation
This paper presents a method of reliability analysis by simulation. Hardware level modularity in creating a simulation model is achieved by use of the VHDL language. Each hardware component is individually modeled in VHDL for calculation of its failure time based on its reliability. VHDL simulation results are compared for common structures with known reliability analysis methods such as Markov model.