{"title":"一个10位50 msps流水线CMOS ADC","authors":"M. Hashim, Y. Yusoff, Mohd Rais Ahmad","doi":"10.1109/SMELEC.2006.381103","DOIUrl":null,"url":null,"abstract":"This paper presents a 10-bit 50-MSPS pipelined ADC targeted to 0.35 um CMOS technology. The main characteristics of pipelined ADC such as signal to noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential non-linearity (DNL), integral non-linearity (INL) and power consumption are simulated in HSPICEreg. In this simulation, a full-scale of Nyquist-frequency sine-wave input is used. The results show the designed pipelined ADC achieves a SNDR of 58 dB, SFDR of 70 dB, maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.5 least significant bit (LSB) and a power consumption of 350-mW.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 10-Bit 50-MSPS Pipelined CMOS ADC\",\"authors\":\"M. Hashim, Y. Yusoff, Mohd Rais Ahmad\",\"doi\":\"10.1109/SMELEC.2006.381103\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 10-bit 50-MSPS pipelined ADC targeted to 0.35 um CMOS technology. The main characteristics of pipelined ADC such as signal to noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential non-linearity (DNL), integral non-linearity (INL) and power consumption are simulated in HSPICEreg. In this simulation, a full-scale of Nyquist-frequency sine-wave input is used. The results show the designed pipelined ADC achieves a SNDR of 58 dB, SFDR of 70 dB, maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.5 least significant bit (LSB) and a power consumption of 350-mW.\",\"PeriodicalId\":136703,\"journal\":{\"name\":\"2006 IEEE International Conference on Semiconductor Electronics\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on Semiconductor Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2006.381103\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on Semiconductor Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2006.381103","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
本文提出了一种针对0.35 um CMOS技术的10位50 msps流水线ADC。在HSPICEreg中模拟了管道ADC的主要特性，如信噪比(SNDR)、无杂散动态范围(SFDR)、微分非线性(DNL)、积分非线性(INL)和功耗。在这个模拟中，使用了一个满量程的奈奎斯特频率正弦波输入。结果表明，所设计的流水线ADC的SNDR为58 dB, SFDR为70 dB，最大差分非线性(DNL)和积分非线性(INL)均小于0.5最低有效位(LSB)，功耗为350 mw。
This paper presents a 10-bit 50-MSPS pipelined ADC targeted to 0.35 um CMOS technology. The main characteristics of pipelined ADC such as signal to noise and distortion ratio (SNDR), spurious free dynamic range (SFDR), differential non-linearity (DNL), integral non-linearity (INL) and power consumption are simulated in HSPICEreg. In this simulation, a full-scale of Nyquist-frequency sine-wave input is used. The results show the designed pipelined ADC achieves a SNDR of 58 dB, SFDR of 70 dB, maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.5 least significant bit (LSB) and a power consumption of 350-mW.
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