R. Berger, A. Bertapelli, R. Frankel, J.J. Hunt, J. Mann, J. Raffel, F. M. Rhodes, A. Soares, C. Woodward
{"title":"林肯可编程图像处理晶片","authors":"R. Berger, A. Bertapelli, R. Frankel, J.J. Hunt, J. Mann, J. Raffel, F. M. Rhodes, A. Soares, C. Woodward","doi":"10.1109/ICWSI.1990.63878","DOIUrl":null,"url":null,"abstract":"The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"25 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"The Lincoln programmable image-processing wafer\",\"authors\":\"R. Berger, A. Bertapelli, R. Frankel, J.J. Hunt, J. Mann, J. Raffel, F. M. Rhodes, A. Soares, C. Woodward\",\"doi\":\"10.1109/ICWSI.1990.63878\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"25 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63878\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63878","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The Programmable Image Processor is a laser-restructurable, wafer-scale device fabricated on a 125-mm wafer using an n-well CMOS process with 2.0 micrometer gates. Yield projections indicate that one wafer has enough devices to construct an array of 16 SIMD-programmable processors and 25 shared memories. The memory array can store two images each 128-by-128 pixels. One run of wafers has been fabricated, and these wafers were undergoing testing and restructuring at the time of publication.<>
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