{"title":"TLM 2.0模型的细化和重用:ESL成功的关键","authors":"Víctor Reyes","doi":"10.1109/VDAT.2009.5158105","DOIUrl":null,"url":null,"abstract":"ESL design methods and tools are being proposed to improve the productivity of the designers and to bridge the design and verification gaps. The main area where ESL solutions are being successfully applied on current desire flows is Virtual Prototyping. The success of these methods relies on the rapidly adoption from Semiconductor industry and EDA vendors of standards such as SystemC and TLM 2.0. Ideally. TLM models must be accurate enough, fast enough and easy to create in order to fit all Virtual Prototype use-cases. However reality shows that different requirements are achieved only by using different type of models (the right model for the right use-case). This is because TLM modeling is a multidimensional problem where the different dimensions (speed, timing accuracy and modeling effort) are orthogonal with each other. Having to create and maintain a separated model for each use-case is drastically reducing the benefits of VP technology, due to elevated cost of creating and maintaining the models consistent with each other. Therefore, model reuse and refinement is a must for the suceess of ESL technology. This paper describes modeling concepts that can be used to create speed optimal models with low effort, which can be gradually refined with more timing accuracy and therefore reused for different VP use-cases.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Refinement and reuse of TLM 2.0 models: The key for ESL success\",\"authors\":\"Víctor Reyes\",\"doi\":\"10.1109/VDAT.2009.5158105\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"ESL design methods and tools are being proposed to improve the productivity of the designers and to bridge the design and verification gaps. The main area where ESL solutions are being successfully applied on current desire flows is Virtual Prototyping. The success of these methods relies on the rapidly adoption from Semiconductor industry and EDA vendors of standards such as SystemC and TLM 2.0. Ideally. TLM models must be accurate enough, fast enough and easy to create in order to fit all Virtual Prototype use-cases. However reality shows that different requirements are achieved only by using different type of models (the right model for the right use-case). This is because TLM modeling is a multidimensional problem where the different dimensions (speed, timing accuracy and modeling effort) are orthogonal with each other. Having to create and maintain a separated model for each use-case is drastically reducing the benefits of VP technology, due to elevated cost of creating and maintaining the models consistent with each other. Therefore, model reuse and refinement is a must for the suceess of ESL technology. This paper describes modeling concepts that can be used to create speed optimal models with low effort, which can be gradually refined with more timing accuracy and therefore reused for different VP use-cases.\",\"PeriodicalId\":246670,\"journal\":{\"name\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Symposium on VLSI Design, Automation and Test\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VDAT.2009.5158105\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Symposium on VLSI Design, Automation and Test","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT.2009.5158105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Refinement and reuse of TLM 2.0 models: The key for ESL success
ESL design methods and tools are being proposed to improve the productivity of the designers and to bridge the design and verification gaps. The main area where ESL solutions are being successfully applied on current desire flows is Virtual Prototyping. The success of these methods relies on the rapidly adoption from Semiconductor industry and EDA vendors of standards such as SystemC and TLM 2.0. Ideally. TLM models must be accurate enough, fast enough and easy to create in order to fit all Virtual Prototype use-cases. However reality shows that different requirements are achieved only by using different type of models (the right model for the right use-case). This is because TLM modeling is a multidimensional problem where the different dimensions (speed, timing accuracy and modeling effort) are orthogonal with each other. Having to create and maintain a separated model for each use-case is drastically reducing the benefits of VP technology, due to elevated cost of creating and maintaining the models consistent with each other. Therefore, model reuse and refinement is a must for the suceess of ESL technology. This paper describes modeling concepts that can be used to create speed optimal models with low effort, which can be gradually refined with more timing accuracy and therefore reused for different VP use-cases.