Implementation of a 16 Phase Digital Modulator in a 0.35 /spl mu/m Process

In this paper we present a custom IC design and experimental results for a hardware efficient 16 phase digital modulator implemented in a 0.35 mum process. The hardware efficient realization is achieved by time sharing the high resolution portion of the modulator hardware and a simple solution to track phase rotation. The modulator is designed for a duty cycle update rate at 16 times the single phase switching frequency to enable wide bandwidth multiphase converter operation. Two versions of the time shared high resolution portion of the IC are realized, including counter based and self tuning delay line based designs. Design details and experimental results are given to evaluate the two options and demonstrate performance of the IC