{"title":"三维图形中的分段多项式函数评估——基于人工智能的新型数字乘法器","authors":"M. Renuka, G. Valantina","doi":"10.1109/ICCSP48568.2020.9182208","DOIUrl":null,"url":null,"abstract":"An Artificial Intelligence based Novel dual-channel multiplier (AINDCM) for the area and power-efficient second-order piecewise- polynomial function evaluation for three-dimensional graphics applications is presented in this paper. In any multiplier, the working of the estimation method is highly dependent on the type of adder structure. Different hardware structures of adders and their implementations are presented. The proposed multipliers overcome the drawbacks of conventional DCM multiplier using Parallel Prefix adders which decrease the hardware difficulty. The proposed scheme performs complex methods with a power- efficient and area-efficient approach. The prefix adders reduce the hardware computational effort in the piecewise polynomial approximation with uniform or non-uniform segmentation. These units accomplish the low power consumption compared to CPA with large input word size. The parameters area, delay, and power will be analyzed and compared.","PeriodicalId":321133,"journal":{"name":"2020 International Conference on Communication and Signal Processing (ICCSP)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Piecewise-Polynomial Function Evaluation in 3-D Graphics- Artificial Intelligence based New Digital Multiplier\",\"authors\":\"M. Renuka, G. Valantina\",\"doi\":\"10.1109/ICCSP48568.2020.9182208\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An Artificial Intelligence based Novel dual-channel multiplier (AINDCM) for the area and power-efficient second-order piecewise- polynomial function evaluation for three-dimensional graphics applications is presented in this paper. In any multiplier, the working of the estimation method is highly dependent on the type of adder structure. Different hardware structures of adders and their implementations are presented. The proposed multipliers overcome the drawbacks of conventional DCM multiplier using Parallel Prefix adders which decrease the hardware difficulty. The proposed scheme performs complex methods with a power- efficient and area-efficient approach. The prefix adders reduce the hardware computational effort in the piecewise polynomial approximation with uniform or non-uniform segmentation. These units accomplish the low power consumption compared to CPA with large input word size. The parameters area, delay, and power will be analyzed and compared.\",\"PeriodicalId\":321133,\"journal\":{\"name\":\"2020 International Conference on Communication and Signal Processing (ICCSP)\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International Conference on Communication and Signal Processing (ICCSP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCSP48568.2020.9182208\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International Conference on Communication and Signal Processing (ICCSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCSP48568.2020.9182208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Piecewise-Polynomial Function Evaluation in 3-D Graphics- Artificial Intelligence based New Digital Multiplier
An Artificial Intelligence based Novel dual-channel multiplier (AINDCM) for the area and power-efficient second-order piecewise- polynomial function evaluation for three-dimensional graphics applications is presented in this paper. In any multiplier, the working of the estimation method is highly dependent on the type of adder structure. Different hardware structures of adders and their implementations are presented. The proposed multipliers overcome the drawbacks of conventional DCM multiplier using Parallel Prefix adders which decrease the hardware difficulty. The proposed scheme performs complex methods with a power- efficient and area-efficient approach. The prefix adders reduce the hardware computational effort in the piecewise polynomial approximation with uniform or non-uniform segmentation. These units accomplish the low power consumption compared to CPA with large input word size. The parameters area, delay, and power will be analyzed and compared.