Chieh-Min Lo, Shih-Fong Chao, Chiajung Chang, Huei Wang
{"title":"采用螺旋堆叠电感的全集成5-6 GHz CMOS可变增益LNA","authors":"Chieh-Min Lo, Shih-Fong Chao, Chiajung Chang, Huei Wang","doi":"10.1109/EMICC.2006.282653","DOIUrl":null,"url":null,"abstract":"This paper presents the design and implementation of a 5-6 GHz CMOS variable-gain low noise amplifier (VGLNA) for IEEE 802.11a WLAN application, fabricated on TSMC 0.18-mum 1P6M standard CMOS process. In this design, miniature chip size and wide gain-control range are achieved by using helix-stacked inductors and current steering technology, respectively. This VGLNA exhibits a noise figure of 3.1 dB, small signal gain of 19 dB, and IIP3 of -9 dBm while in its high gain mode. A gain of -19 dB with IIP3 of -4 dBm were measured while switching into its low gain mode. The chip size is only 0.56 mm2","PeriodicalId":269652,"journal":{"name":"2006 European Microwave Integrated Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A Fully Integrated 5-6 GHz CMOS Variable-Gain LNA Using Helix-stacked Inductors\",\"authors\":\"Chieh-Min Lo, Shih-Fong Chao, Chiajung Chang, Huei Wang\",\"doi\":\"10.1109/EMICC.2006.282653\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design and implementation of a 5-6 GHz CMOS variable-gain low noise amplifier (VGLNA) for IEEE 802.11a WLAN application, fabricated on TSMC 0.18-mum 1P6M standard CMOS process. In this design, miniature chip size and wide gain-control range are achieved by using helix-stacked inductors and current steering technology, respectively. This VGLNA exhibits a noise figure of 3.1 dB, small signal gain of 19 dB, and IIP3 of -9 dBm while in its high gain mode. A gain of -19 dB with IIP3 of -4 dBm were measured while switching into its low gain mode. The chip size is only 0.56 mm2\",\"PeriodicalId\":269652,\"journal\":{\"name\":\"2006 European Microwave Integrated Circuits Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 European Microwave Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMICC.2006.282653\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 European Microwave Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMICC.2006.282653","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Fully Integrated 5-6 GHz CMOS Variable-Gain LNA Using Helix-stacked Inductors
This paper presents the design and implementation of a 5-6 GHz CMOS variable-gain low noise amplifier (VGLNA) for IEEE 802.11a WLAN application, fabricated on TSMC 0.18-mum 1P6M standard CMOS process. In this design, miniature chip size and wide gain-control range are achieved by using helix-stacked inductors and current steering technology, respectively. This VGLNA exhibits a noise figure of 3.1 dB, small signal gain of 19 dB, and IIP3 of -9 dBm while in its high gain mode. A gain of -19 dB with IIP3 of -4 dBm were measured while switching into its low gain mode. The chip size is only 0.56 mm2
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