Novel curve fitting design methodology for carbon nanotube SRAM cell optimization

Unlike CMOS circuit design, even though there are promising advantages to use carbon nanotubes for digital circuits in terms of power, delay, temperature, and area, one of the critical issues to design by using carbon nanotubes is optimization of additional design parameters such as number of nanotubes and pitch size. To reduce the optimization complexity of the increased technology parameters, in this paper, we proposed a novel curve fitting design methodology for carbon-nanotube circuits. The proposed curve fitting methodology can guarantee from 90% to 100% correlation accuracy comparing with SPICE simulation and it can find optimal CNFET SRAM cell parameters without exhaustive simulation time and large memory space. The optimized CNFET SRAM cell by the proposed methodology shows that total power consumption including static power is reduced by 83.14% and the total PDP (product of delay and power) is reduced by 83.39%, comparing with CMOS SRAM cell design. The total runtime is reduced by 96.9% compared with conventional Monte Carlo simulation method in SPICE.