Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee
{"title":"二维DWT系统架构的设计空间探索","authors":"Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee","doi":"10.1109/ICCIS.2010.5518584","DOIUrl":null,"url":null,"abstract":"This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.","PeriodicalId":445473,"journal":{"name":"2010 IEEE Conference on Cybernetics and Intelligent Systems","volume":"226 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design space exploration of a 2-D DWT system architecture\",\"authors\":\"Ishmael Sameen, Yoong Choon Chang, N. Song, B. Goi, Chee Siong Lee\",\"doi\":\"10.1109/ICCIS.2010.5518584\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.\",\"PeriodicalId\":445473,\"journal\":{\"name\":\"2010 IEEE Conference on Cybernetics and Intelligent Systems\",\"volume\":\"226 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-06-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Conference on Cybernetics and Intelligent Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCIS.2010.5518584\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Conference on Cybernetics and Intelligent Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIS.2010.5518584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
摘要
提出了一种基于JPEG-2000标准的可编程二维DWT系统体系结构。所提出的系统架构源自使用Altera的C2H编译器的迭代设计空间探索过程，与优化的二维DWT软件实现相比，提供了显著的二维DWT性能加速，并且在Altera DE3 Stratix III FPGA板上合成和测试时能够实现高达720p (1280 × 720)图像分辨率的实时视频处理性能。
Design space exploration of a 2-D DWT system architecture
This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance up to 720p (1280 × 720) image resolutions when synthesized and tested on an Altera DE3 Stratix III FPGA board.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
