{"title":"一种人工优化的(15,4)并行计数器设计","authors":"Qihang Jiang, Shuguo Li","doi":"10.1109/EDSSC.2017.8126527","DOIUrl":null,"url":null,"abstract":"This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.","PeriodicalId":163598,"journal":{"name":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","volume":"237 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A design of manually optimized (15, 4) parallel counter\",\"authors\":\"Qihang Jiang, Shuguo Li\",\"doi\":\"10.1109/EDSSC.2017.8126527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.\",\"PeriodicalId\":163598,\"journal\":{\"name\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"volume\":\"237 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2017.8126527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2017.8126527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A design of manually optimized (15, 4) parallel counter
This paper mainly presents a design of optimized (15, 4) parallel counter. When testing the design with 15 rows of inputs, synthesis report of our design performs better in respect of delay, area and power consumption than other two existing design. This result shows that processes such as partial product reduction in a multiplier or column-addition in a matrix could be more efficient, especially when those signals arrive in parallel.
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