The development of the global feature extractor for the LHC Run-3 upgrade of the L1 calorimeter trigger system

The Global Feature Extractor (gFEX) is one of several modules in the LHC Run-3 upgrade of the Level 1 Calorimeter (L1Calo) trigger system in the ATLAS experiment. It is a single Advanced Telecommunications Computing Architecture (ATCA) module for large-area jet identification with three Xilinx Virtex UltraScale FPGAs for data processing and a system-on-chip (SoC) FPGA for control and monitoring. A pre-prototype board has been designed to verify all functionalities, which includes one Xilinx Virtex-7 FPGA, one Zynq FPGA, several MiniPODs, MicroPODs, DDR3 SDRAM and other components. The performance of the pre-prototype has been tested and evaluated. As a major challenge, the high-speed links in FPGAs are stable at 12.8 Gb/s with Bit Error Ratio (BER) <; 10-15 (no error detected). The low-latency parallel GPIO (General Purpose I/O) buses for communication between FPGAs are stable at 960 Mb/s. The peripheral components of Zynq FPGA like DDRs, UART, SPI flashes, Ethernet and so on, have also been verified. The test results of the pre-prototype board validate the gFEX technologies and architecture. Now the prototype board with three UltraScale FPGAs is on the way.