Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs

This work presents a full chip thermal analysis of 2-D high performance ICs based on technological, structural, and material data from ITRS '99. It is shown that interconnect Joule heating in advanced technology nodes can strongly impact the magnitude of the maximum temperature within 2-D chips despite negligible change in the chip power density, as per the ITRS. This result has been shown to have significant implications for interconnect reliability and performance not foreseeable by the ITRS. Furthermore, detailed thermal analysis of vertically integrated (3-D) ICs has been carried out using analytical modeling and numerical simulations. Additionally, comparison between the thermal design of two alternative 3-D technologies has been presented for the first time using ITRS data.