High datarate rate regulated 4D 8PSK-TCM implementation in FPGA for satellite

With the increase in camera resolution or usage of SAR payload in remote sensing satellite, demand for high data rate transmission has increased in a given bandwidth. This has also forced to use higher modulation like 8 PSK over QPSK to accommodate higher data rate in the same bandwidth. A typical usage is 1.2Gbps data rate transmission scheme using 8PSK dual polarization in x-Band, having bandwidth of 375Mhz. Higher modulation scheme demands higher power to maintain the link margin. Alternative to the higher power is to use a suitable channel coding scheme. 4D 8PSK-TCM is a channel coding scheme suitable for 8PSK modulation [1]. The coding scheme supports Spectral Efficiencies of 2, 2.25, 2.5 & 2.75 bits/channel-symbol. Challenges exist in implementation of these different code rates in a single architecture as it demands rate buffer implementation to provide seamless transmission that is difficult to realize without the use of FPGA. The paper addresses the difficulties in implementation especially when the 4D 8PSK-TCM module is inserted in Data-link layer. The solution to these difficulties is implementation of a suitable rate regulator for various code rate of 4D 8PSK-TCM in FPGA for high datarate (~ 600Mbps) application. The paper also addresses 4D-TCM usages in data link layer of satellite transmission system.