T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa
{"title":"在16nm工艺节点上详细的寄生电容分析研究了FinFET的面积和性能","authors":"T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa","doi":"10.1109/ICMTS.2015.7106125","DOIUrl":null,"url":null,"abstract":"An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.","PeriodicalId":177627,"journal":{"name":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node\",\"authors\":\"T. Okagaki, K. Shibutani, H. Matsushita, H. Ojiro, M. Morimoto, Y. Tsukamoto, K. Nii, K. Onozawa\",\"doi\":\"10.1109/ICMTS.2015.7106125\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.\",\"PeriodicalId\":177627,\"journal\":{\"name\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2015 International Conference on Microelectronic Test Structures\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2015.7106125\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2015 International Conference on Microelectronic Test Structures","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2015.7106125","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Area and performance study of FinFET with detailed parasitic capacitance analysis in 16nm process node
An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a delay cell because it is easy to increase delay time with simple layout modification only. Moreover, small number of delay cell can reduce a leakage current in a chip.
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