用于模拟VLSI可编程神经网络的低功耗CMOS电路

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) Pub Date : 1900-01-01 DOI:10.1109/ICM.2003.238250

M. El-Soud, R. Abdelrassoul, H. Soliman, L. El-ghanam

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引用次数: 4

摘要

本文提出了一种用于设计可编程神经系统的模拟VLSI神经网络。在三极管区域使用四个mos晶体管设计突触权重。在阈下区域设计了和元和激活函数。本系统采用标准的0.8 /spl μ m CMOS工艺，采用1 /spl plusmn/1V电源运行。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low-power CMOS circuits for analog VLSI programmable neural networks

This paper presents an analog VLSI neural network for designing a programmable neural system. Synaptic weights are designed in the triode region using four-MOS transistors. Moreover, the summing element (SE) and the activation function are designed in subthreshold region. This system is realized in a standard 0.8 /spl mu/m CMOS technology and operated with a /spl plusmn/1V power supply.

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Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442)

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