{"title":"通过逻辑关联减轻基于缓存争用的攻击","authors":"Xiao Liu, Mark Zwolinski","doi":"10.1109/prime55000.2022.9816809","DOIUrl":null,"url":null,"abstract":"Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.","PeriodicalId":142196,"journal":{"name":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Mitigating Cache Contention-Based Attacks by Logical Associativity\",\"authors\":\"Xiao Liu, Mark Zwolinski\",\"doi\":\"10.1109/prime55000.2022.9816809\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.\",\"PeriodicalId\":142196,\"journal\":{\"name\":\"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/prime55000.2022.9816809\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/prime55000.2022.9816809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Mitigating Cache Contention-Based Attacks by Logical Associativity
Many cache designs have been proposed to guard against last-level cache, contention-based, side-channel attacks. One of the most well-known implementations, CEASER-S, applies an encryption cypher with a periodically changing key as a cache indexing function. By increasing the re-keying frequency, CEASER-S can defeat an attack. However, this can lead to performance degradation. In this paper, we propose cache logical associativity. By combining this approach with CEASER-S, our cache, CEASER-SH, sacrifices less performance while maintaining the same security level against more advanced contention-based side-channel attacks. For example, compared with CEASER-S, CEASER-SH with a logical associativity of 3 can reduce the miss rate degradation by about 30% and that of the CPI by 1% while maintaining the same security level against a strong Prime+Probe attack.