{"title":"用于高速数模转换器的数字自补偿电路","authors":"Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim","doi":"10.1109/VLSIC.1994.586160","DOIUrl":null,"url":null,"abstract":"This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.","PeriodicalId":350730,"journal":{"name":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Digital Self Compensation Circuit for High Speed D/a Converters\",\"authors\":\"Ook Kim, Jungwook Yang, Suk-ki Kim, Wonchan Kim\",\"doi\":\"10.1109/VLSIC.1994.586160\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.\",\"PeriodicalId\":350730,\"journal\":{\"name\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1994.586160\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1994.586160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Digital Self Compensation Circuit for High Speed D/a Converters
This paper presents a digital self compensation method for video-rate D/A converters(DAC's). In this method, the compensation operation is isolated from the high speed operation of the current switch. Therefore, the errors of each element of the device can be corrected without interrupting the device operation. This method was implemented using standard 0.8 pnt CMOS technology. The measured Integral Nonlinearity of the IO-bit CMOS DAC decreased to 0.22LSB.
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