{"title":"一个1.5 V，单电源，单晶体管CMOS EEPROM","authors":"B. Gerber, J. Martin, J. Fellrath","doi":"10.1109/ESSCIRC.1980.5468761","DOIUrl":null,"url":null,"abstract":"A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been developed. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104-105 cycles.","PeriodicalId":168272,"journal":{"name":"ESSCIRC 80: 6th European Solid State Circuits Conference","volume":"99 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1980-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM\",\"authors\":\"B. Gerber, J. Martin, J. Fellrath\",\"doi\":\"10.1109/ESSCIRC.1980.5468761\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been developed. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104-105 cycles.\",\"PeriodicalId\":168272,\"journal\":{\"name\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"volume\":\"99 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1980-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 80: 6th European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1980.5468761\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 80: 6th European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1980.5468761","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.5 V, Single-Supply, One-Transistor CMOS EEPROM
A 1.5 V, single-supply, one-transistor p-ch CMOS EEPROM array has been developed. Negative write and erase voltages of -28V are generated on-chip by voltage multipliers and fed by a 1.5 V logic to the matrix array. Erase and writing times are 25 ms. Endurance is 104-105 cycles.
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