混合忆阻- mos异或与异或逻辑门的设计

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC) Pub Date : 2017-10-01 DOI:10.1109/EDSSC.2017.8126414

Xiaoyan Xu, Xiaole Cui, M. Luo, Qiujun Lin, Yichi Luo, Yufeng Zhou

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引用次数: 10

摘要

提出了两种基于忆阻比逻辑(MRL)的忆阻- mos非相容或(XOR)和非相容或(XNOR)混合逻辑门。所提出的门以电压呈现逻辑状态，并在一个时钟周期内实现逻辑运算。该设计缓解了原始MRL逻辑门的电压退化问题，同时消耗更少的面积开销和更小的延迟。

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Design of hybrid memristor-MOS XOR and XNOR logic gates

Two hybrid memristor-MOS exclusive OR (XOR) and exclusive NOR (XNOR) logic gates based on Memristor Ratioed Logic (MRL) are presented. The proposed gates present logic states with voltages, and implement the logic operation within one clock cycle. The designs ease the voltage degradation problem of the original MRL logic gates, while consuming fewer area overhead and less delay than their counterparts.

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2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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