M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi
{"title":"一种设计Smith图级间匹配网络的新方法","authors":"M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi","doi":"10.1109/SMELEC.2006.380742","DOIUrl":null,"url":null,"abstract":"In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.","PeriodicalId":136703,"journal":{"name":"2006 IEEE International Conference on Semiconductor Electronics","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Novel Method to Design Interstage Matching Network in the Smith Chart\",\"authors\":\"M. R. Abkenari, M. Tayarani, A. Abdipour, H. Kiumarsi\",\"doi\":\"10.1109/SMELEC.2006.380742\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.\",\"PeriodicalId\":136703,\"journal\":{\"name\":\"2006 IEEE International Conference on Semiconductor Electronics\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Conference on Semiconductor Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2006.380742\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Conference on Semiconductor Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2006.380742","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Method to Design Interstage Matching Network in the Smith Chart
In this paper, a novel method for interstage matching network design in the smith chart is presented. This technique is based on matching the reflection coefficients between input of interstage matching network and S22 of the first transistor with considering input VSWR and the gain of the complete amplifier (or output of the complete amplifier if the matching is applied to the output of the interstage matching network). Also, the novel locus of constant gain and VSWR of interstage matching network are presented in the smith chart.
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